I’m able to user Timer 4 to trigger EDMA using the technique described in http://e2e.ti.com/support/arm/sitara_arm/f/791/t/359154. My application uses Timer 4 to count external pulses (TCLKIN) then triggers EDMA using the compare (TMAR) register. One of the DMA chains updates Timer 4 TCRR to set the number of input pulses to count until the next match. It appears there’s a 2 clock pipeline delay between when the compare occurs until the new TCRR value written by the EDMA takes effect.
The following sequence describes what’s happening. The external Timer 4 clock input is 20Khz (slow). Each step below represents a new clock input transition. Initial conditions for this example are TMAR = 20 and TCRR = 19. This should generate a match (and EDMA) every 2 clock pulses but it actually takes 4.
-
TCRR increments to 20. Internally, Timer 4 does not detect the match until the next clock.
-
TCRR increments to 21. Timer 4 detects prior TCRR matches TMAR. Timer 4 sets trigger output pulse high and EDMA is triggered which writes 19 to TCRR. EDMA finished before next clock.
-
TCRR advances to 22. Timer 4 sets trigger output pulse low.
-
TCRR is finally loaded with 19 set by EDMA in step 2. On next clock, repeat starting at step 1.
So how am I able to tell TCRR runs past 20? I have a tight code loop that continuously reads TCRR and sets 3 GPIO signals indicating the value (20, 21, 22).
So getting back to my goal, how can I initiate EDMA every 1-N input pulses? Right now I can only do 3-N pulses. I need the DMA to change the number of pulses the timer counts until the next EDMA, without a padding of 2 clocks like it does now.
I tried updating TMAR instead of TCRR or using Timer 4 overflow but I still can’t get below 3 input clock transitions between EDMAs. There appears to be pipeline delays in the timer. I’m presently using POSTED mode (bit set in TSICR). My understanding is POSTED READ/WRITE is related to the internal OCP clock, not external clock.
