Am335x SPI Master DO signal too low

michael musset

Hi,

How do you configure the PINS correctly ? I heard that you have to put RXACTIVE=1 for the SCLK signal ( which doesn't make sense ) .

My problem is the output from the spi master, the signal doesn't get above 1.12V And I don't know why ? I have only a pull up resistor between the am335X SPI DO and the max3107 SPI DI .

my config :

0x164 0x24 /* (C18) eCAP0_in_PWM0_out.spi1_sclk ok*/
0x168 0x0C /* (E18) uart0_ctsn.spi1_d0 */
0x16c 0x14 /* (E17) uart0_rtsn.spi1_d1 */
0x170 0x11 /* (E15) uart0_rxd.spi1_cs0 */
0x174 0x11 /* (E16) uart0_txd.spi1_cs1 */

Any Idea ?

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

michael musset said:
How do you configure the PINS correctly ? I heard that you have to put RXACTIVE=1 for the SCLK signal ( which doesn't make sense ) .

Read Note 1 below Table 24-4 in the AM335X TRM Rev. M.

michael musset said:

my config :

0x164 0x24 /* (C18) eCAP0_in_PWM0_out.spi1_sclk ok*/
0x168 0x0C /* (E18) uart0_ctsn.spi1_d0 */
0x16c 0x14 /* (E17) uart0_rtsn.spi1_d1 */
0x170 0x11 /* (E15) uart0_rxd.spi1_cs0 */
0x174 0x11 /* (E16) uart0_txd.spi1_cs1 */

Please check the value of MCSPI_CHxCONF register (TRM Section 24.4.1.8). Pay attention to bitfields IS, DPE0, DPE1. Also check for external issues that could pull D0 signal down.

0 Biser Gatchev-XID over 9 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

One more thing: in your pinmux you have disabled the receiver on both D0 and D1.

0 michael musset over 9 years ago in reply to Biser Gatchev-XID

Expert 1135 points

Yes,

It looks like I shouldn't have look at what other do ^^ , because some of them choose spi in mode slave or spi in master mode.

After a deep learning of the pin configuration, i'm going with this mode :

0x164 0x0C (C18) eCAP0_in_PWM0_out.spi1_sclk ok*/
0x168 0x0C (E18) uart0_ctsn.spi1_d0 */
0x16c 0x2C (E17) uart0_rtsn.spi1_d1 */
0x170 0x03 (E15) uart0_rxd.spi1_cs0 */
0x174 0x03 (E16) uart0_txd.spi1_cs1 */

0 Biser Gatchev-XID over 9 years ago in reply to michael musset

TI__Guru**** 393215 points

0x164 0x0C (C18) eCAP0_in_PWM0_out.spi1_sclk ok*/

Should be:

0x164 0x2C (C18) eCAP0_in_PWM0_out.spi1_sclk ok*/

0 michael musset over 9 years ago in reply to Biser Gatchev-XID

Expert 1135 points

why the clock will be an input ? the clock is generated from the master, not from the slave ... that's something that i don't get it !

0 Biser Gatchev-XID over 9 years ago in reply to michael musset

TI__Guru**** 393215 points

Read Note 1 below Table 24-4 in the AM335X TRM Rev. M. It says:

"This output signal is also used as a re-timing input. The associated CONF_<module>_<pin>_RXACTIVE bit for the output clock
must be set to 1 to enable the clock input back to the module."

0 Biser Gatchev-XID over 9 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

I already posted this above in this thread.

0 michael musset over 9 years ago in reply to Biser Gatchev-XID

Expert 1135 points

Thx for the tips about the register, I checked where the driver write to the register to configure the spi and I found those lines :

902 if (mcspi->pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT) {
903 l &= ~OMAP2_MCSPI_CHCONF_IS;
904 l &= ~OMAP2_MCSPI_CHCONF_DPE1;
905 l |= OMAP2_MCSPI_CHCONF_DPE0;
906 } else {
907 l |= OMAP2_MCSPI_CHCONF_IS;
908 l |= OMAP2_MCSPI_CHCONF_DPE1;
909 l &= ~OMAP2_MCSPI_CHCONF_DPE0;
910 }

I put a printk and I discovered that pin_dir == MCSPI_PINDIR_D0_IN_D1_OUT

which is wrong, so I put a new line in the spi device tree file :
ti,pindir-d0-out-d1-in;

But I don't understand why D1 is out by default .....

do you think that my understanding is correct ?

0 Biser Gatchev-XID over 9 years ago in reply to michael musset

TI__Guru**** 393215 points

Yes, this should do it. About default config, this is because SPI pins are initialized by ROM code this way (D0 - MISO, D1 - MOSI).

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Am335x SPI Master DO signal too low