UART Flag check for receiving byte stream

Sherry Ismail

System: C6748, LCDKC6748. SYS BIOS used.

I have a stream of 4096 bytes incoming from a host into UART port. Currently, my UART Interrupt Service Routine is receiving all the byte stream inside the Hwi-ISR., using a for loop and a counter

What flag should I use to distinguish between two consecutive bytes ?LSR[DR] flag or IIR[INTID]??

The problem is that all interrupts are masked once UART enters the ISR and technical reference manual suggests that above mentioned flags will be set only if their corresponding bits in IER are enabled. This is my code now

int j = 0;
	for (i = 0; i < loopSize; i++) {	//Loopsize = 1024
		COEFFS_L[i] = 0;				
		for (j = (wordSize - 1); j >= 0; j--) {	//wordsize = 4 for a 32-bit value
			USTIMER_delay(120);					// CPU waits between two consecutive bytes
			rxByte[0] = UART2Read();			// Read from RBR register
			COEFFS_L[i] |= ((int32_t) rxByte[0] << (j * 8));	//Received MSB first LSB later, left shift byte per byte
		}
	}

If there is no other choice, i could push the routine of receiving byte stream into SWI or Task, using my own set of flags in the program. But if there is a flag that toggles as RBR register is getting filled (even when Interrupts are held), that would be great :)
For example, instead of delay function, could i use?

while(uart2->LSR & 0x00000001 == 0);

over 9 years ago

0 Sherry Ismail over 9 years ago

Intellectual 885 points

My UART received data gets corrupted when Host is busy and has longer delay than 120usec between two consecutive bytes. instead of a fixed delay, i would like to check a flag that tells if RBR is receiving a new byte.

0 Sivaraj Kuppuraj over 9 years ago in reply to Sherry Ismail

TI__Mastermind 35645 points

Hi,

We will work on your request and get back to you at the earliest.

Thanks & regards,
Sivaraj K

0 Sivaraj Kuppuraj over 9 years ago in reply to Sivaraj Kuppuraj

TI__Mastermind 35645 points

Hi,

Yes you are correct. You could use LSR in which if the DR bit is set and the corresponding interrupt enable bit is set (ERBI = 1 in IER), an interrupt request would be generated which indicates the data ready for the receiver. Refer Table 30-17 from the TRM below:

I think, there is a ERBI field in IER which can be enabled so that it gives the provision to enable receiver data available interrupt and character timeout indication interrupt. Kindly refer Table 30-9 from the TRM below:

http://www.ti.com/lit/ug/spruh79a/spruh79a.pdf

As well, in the non-FIFO mode, when a character is placed in RBR and if the receiver data-ready interrupt is enabled in IER, an interrupt would be generated. This interrupt would be cleared when the character is read from RBR.

In the FIFO mode, the same interrupt would be generated when the FIFO is filled to the trigger level selected in the FIFO control register, and it would be cleared when the FIFO contents drops below the trigger level. For more info. kindly refer section 30.3.1 from the above doc.

The above would the feasibility check flag fields which would tell if RBR is receiving a new byte or not.

Thanks & regards,

Sivaraj K

------------------------------------------------------------------------------------------------------

Please click the Verify Answer button on this post if it answers your question

-------------------------------------------------------------------------------------------------------

0 Sherry Ismail over 9 years ago in reply to Sivaraj Kuppuraj

Intellectual 885 points

Thank you.
Can I use this flag if the ERBI bit in IER is set to zero? I have IER[ERBI] = 0 inside an ISR where I am receiving a byte stream.

Processors

Processors forum

UART Flag check for receiving byte stream