Dear,
I met some problems while developing DSP optimization on c674x of DM8148.
Hope get some helps.
The question as follows:
When the fist stage of optimization,I use memcpy to complish the data transfer between L2 and DDR3,the code can get correct results.
In order to improve the algorithm speed,using EDMA_transfer() replaces every memcpy functions,but the results become incorrect.
Notes(I write EDMA3_transfer function by myself.)
At the beginning I think EDMA_transfer function maybe have some problems,but I trace the code with data set several time,I cannot find any
error for data movement(tracing code step by step).
The specific data path as follows:
DDR3(cached) --> L2(SRAM,not cached)-->DDR3(cached)
That is, data from DDR3,which is cached by MARn register,to L2(L2 part is L2 SRAM,not used as cache),
then data are processed in L2 SRAM,after processing finished,the results is sent to DDR3(cached).
I know cache coherence must be kept when using EDMA transfer.
In this situation (DDR3(cached) --> L2(SRAM,not cached)-->DDR3(cached) ),how to keep data coherence on C674x dsp.
could you give me some suggestions?
Thank you very much.
BRS,
Meng
