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GPIO[7..0] On DM648

James Gort
Intellectual 590 points

Hi All-

I am very confused by what I am seeing on low GPIO on DM648. I have UHPIEN tied high (and verifed that the 648 indeed sees it as high--UHPI bit in BOOTCFG reg is 1), to enable the low GPIO instead of the PCI interface signals. All of the low GPIOs are unconnected on my hardware platform (no external pull-ups or pull-downs). From the DM648 data sheet, GPIO 7 and 4 have internal pull-ups, and the other low GPIO have internal pulldowns.

However, after reset, I set power and clock to GPIOs, set all the GPIOs to inputs, and read them, I am getting 0xFF on the low GPIOs instead of the expected 0x90. Looking at the gpio registers, DIR01[7..0]=0xFF, and IN_DAT01[7..0]=0xFF. When I subsequently configure them as outputs, and set them high or low, IN_DAT01[7..0] correctly reflects the state I set them to. I cannot scope the actual values on the GPIO signals, as they are not routed from the BGA.

On a different platform, where again UHPIEN is high and I actually use GPIO2 and GPIO3 but they have no external pull-ups or pull-downs, I looked at them with scope after power-on with no boot. Indeed, they were both high, not low as they should have been due to their rumored "internal pull-down".

Can anyone help me understand what is going on here? Is the data sheet wrong (it seems to me GPIO[7..0] all have internal pull ups)? Or are the internal pull-ups/pull-downs different depending on whether PCI interface or UHPI/GPIO is muxed to them?

Thanks in advance,

Jim Gort

 

  • 0
    TI__Genius 16906 points

    Jim,

    At first glance, this does appear to be a documentation typo.  Let me research the design specifications to see exactly what was implemented.

    Thanks,

    Brad

  • 0 in reply to B.C.
    TI__Genius 16906 points

    Jim,

    I was able to confirm the behavior you are seeing by monitoring the GP01 pin on the DM648 EVM.  I also confirmed with our design team that these pins do not have PULL UP capability, only PULL DOWN capability.  Therefore, it could be the case that the internal pull down on these pins is not being enabled for some reason, and the pins are floating to a HIGH value.  This will take some additional work on my side to debug, but I'll get back to you when I have more information.  In the mean time, is this currently causing a problem in your system that I can help you find a work around to?

    Regards,

    Brad

  • 0 in reply to B.C.
    Intellectual 590 points

    Hi Brad-

    Thank you for looking into this.

    The reason why I am concerned about this is we are using GPIO[4..3] in our NEW rev boards to set the "hardware rev" via external pull-up/pull-downs. We did not implement this on the existing "rev 0" boards, so we assumed we would read 10 on [4..3] due to internal pull-up and pull-down per the DM648 data sheet. On the new boards, we are setting them to 01. So..... the fact that I am reading 11 instead of the expected 10 on the old boards (with no external resistors) is not in itself a problem, as long as I have reason to belive that I will ALWAYS read 11 on ALL of the rev0 boards.

    Best Regards,

    Jim

  • 0 in reply to James Gort
    TI__Genius 16906 points

    Jim,

    I've confirmed with the design team that the internal pull resistors on these pins are NEVER enabled.  I'll have the datasheet updated to reflect this.  This means that with no EXTERNAL pulls on these pins, they will be floating when configured as inputs.  Depending on process variation, temperature, voltage, etc. these pins could potentially float LOW (logic 0) in some cases.  Therefore, it is recommended to use external pull resistors on these pins if they are configured as inputs with no external source actively driving them.

    Regards,

    Brad

    PS: Please mark this post as answered via the Verify Answer button below if you think it answers your question.  Thanks!

  • 0 in reply to B.C.
    Intellectual 590 points

    Hi Brad-

    Thanks again for looking into this. Just to be clear, the pins missing internal pull-ups/pull-downs are ONLY GPIO[7..0], or all GPIO, or all PCI/UHPI_GPIO pins?

    Jim

  • 0 in reply to James Gort
    TI__Genius 16906 points

    Jim,

    I've confirmed that all of the PCI-muxed pins are missing the internal pull-up/downs shown in the datasheet.  You will need to use external resistors where needed in your system.

    Regards,

    Brad

    PS: Please mark this post as answered via the Verify Answer button below if you think it answers your question.  Thanks!