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question of a dual rank design for C6678

bing zhou
Prodigy 130 points

Hi Sir

I have two questions

1.There are 4 combination for DDRSLRATE[1:0],(fastest,fast,low,lowest)，i want to know How many differences in memory actually read and write speed with different parameters（fastest,fast,low,lowest）.

2.we use eight pcs twin-die memory components(MT41K1G8TRF-125) for C6678,five on top(ECC)on bot for PCB layout,please help to recommed the routing trace for us,Layout1 and Layout2 which is better？another question，DDRCLKOUT1 can be disconnected？thanks！

  • 0
    Prodigy 130 points
    2.we use eight pcs twin-die memory components(MT41K1G8TRF-125) for C6678,five on top(ECC)and for on bot for PCB layout,please help to recommed the routing trace for us,Layout1 and Layout2 which is better？another question，DDRCLKOUT1 can be disconnected？thanks！
  • 0 in reply to bing zhou
    TI__Mastermind 46460 points

    We actually recommend that you keep all of the SDRAMs on a single layer.  It is much easier to meet the routing rules with that arrangement and allows the minimum number of layers.  Your layout 1 is closest to the linear topology with the routing effectively folded under.  This should be possible but I am not aware that it has been successfully implemented.  Make sure the fly-by spacing at the 'fold' is about the same distance as between the other SDRAMs.  We do not believe that you can meet the routing rules with layout 2 although I believe some customers have done this with mixed success.  Both layout 1 and layout 2 will require additional layers.  It is not acceptable to violate the routing rules and then claim insufficient PCB space.  It is very important that the rules are met.

    Tom