Hi.
I'm using a QDMA channel for transfer data between buffers in MSMCRAM.
when I'm triggering the QDMA using the writing to word 7 in paramset 1.
1) The bit in the QER is not getting '1'.
2) The interrupt bit in the IPR is not comes to '1' as well.
So i'm stack in an endless loop waiting for the IPR bit to come '1'.
need Help !!,
Here is my source code
==========================================================================
#include <stdio.h>
#include <ti/csl/soc.h>
#include <ti/csl/csl_edma3.h>
#include <ti/csl/csl_edma3Aux.h>
#include <ti/csl/csl_cacheAux.h>
#define CSL_EDMA3_CC (2)
#define NUMBER_OF_REGULAR_DMA_CHANNELS (64)
#define QDMA_CHANNEL_TO_DMA_CHANNEL(_X) (_X | NUMBER_OF_REGULAR_DMA_CHANNELS)
/* Global Buffers (Source and Destination) */
#define BUFFER_LENGTH_BYTES (512)
Uint8 srcBuff1[BUFFER_LENGTH_BYTES];
Uint8 srcBuff2[BUFFER_LENGTH_BYTES];
Uint8 dstBuff1[BUFFER_LENGTH_BYTES];
Uint8 dstBuff2[BUFFER_LENGTH_BYTES];
static Bool Verify_Transfer
(
Uint16 aCnt,
Uint16 bCnt,
Uint16 cCnt,
Uint16 srcBIdx,
Uint16 dstBIdx,
Uint16 srcCIdx,
Uint16 dstCIdx,
Uint8 *srcBuff,
Uint8 *dstBuff,
Bool abSync
)
{
Uint32 loopIndex1;
Uint32 loopIndex2;
Uint32 loopIndex3;
Uint8* srcArrayPtr = (Uint8*)srcBuff;
Uint8* dstArrayPtr = (Uint8*)dstBuff;
Uint8* srcFramePtr = (Uint8*)srcBuff;
Uint8* dstFramePtr = (Uint8*)dstBuff;
Uint16 key;
/* Invalidate the cache before verification */
/* Disable Interrupts */
key = _disable_interrupts();
CACHE_invL1d ((void *)srcBuff, 512, CACHE_WAIT);
CACHE_invL2 ((void *)srcBuff, 512, CACHE_WAIT);
CACHE_invL1d ((void *)dstBuff, 512, CACHE_WAIT);
CACHE_invL2 ((void *)dstBuff, 512, CACHE_WAIT);
_mfence();
/* Re-enable Interrupts. */
_restore_interrupts(key);
for (loopIndex1 = 0; loopIndex1 < cCnt; loopIndex1++) {
for (loopIndex2 = 0; loopIndex2 < bCnt; loopIndex2++) {
for (loopIndex3 = 0; loopIndex3 < aCnt; loopIndex3++)
if (srcArrayPtr[loopIndex3] != dstArrayPtr[loopIndex3])
return FALSE;
srcArrayPtr = srcArrayPtr + srcBIdx;
dstArrayPtr = dstArrayPtr + dstBIdx;
}
if (abSync) {
srcFramePtr = srcFramePtr + srcCIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstFramePtr + dstCIdx;
dstArrayPtr = dstFramePtr;
}
else {
srcFramePtr = srcArrayPtr + srcCIdx - srcBIdx;
srcArrayPtr = srcFramePtr;
dstFramePtr = dstArrayPtr + dstCIdx - dstBIdx;
dstArrayPtr = dstFramePtr;
}
}
return TRUE;
}
//#define USE_PRINTS
#define QDMA_CHANNEL_USED (0)
#define PARAMSET_USED (1)
int main(void)
{
CSL_Edma3Context context;
CSL_Edma3Handle hModule;
CSL_Edma3Obj edmaObj;
CSL_Edma3ChannelHandle hChannel;
CSL_Edma3ChannelObj channelObj;
CSL_Edma3ChannelAttr channelAttr;
CSL_Edma3CmdDrae regionAccess;
CSL_Edma3CmdQrae qraeSetup;
CSL_Status status;
CSL_Edma3ParamHandle hParamPing;
CSL_Edma3ParamSetup myParamSetup;
CSL_Edma3CmdIntr regionIntr;
Uint32 loopIndex;
Bool isQer;
Uint8 triggerWord;
Uint16 paramSetNum;
/* Initialize data */
for (loopIndex = 0; loopIndex < 256; loopIndex++) {
srcBuff1[loopIndex] = loopIndex;
srcBuff2[loopIndex] = loopIndex;
dstBuff1[loopIndex] = 0;
dstBuff2[loopIndex] = 0;
}
/* Module initialization */
if (CSL_edma3Init(&context) != CSL_SOK)
{
printf ("Error: EDMA module initialization failed\n");
return -1;
}
/* Module level open */
hModule = CSL_edma3Open(&edmaObj,CSL_EDMA3_CC,NULL,&status);
if ((hModule == NULL) || (status != CSL_SOK))
{
printf ("Error: EDMA module open failed\n");
return -1;
}
else
{
printf ("\nModule Opened\n");
}
/*
// Set the memory protection attributes of region 0.
CSL_edma3SetMemoryProtectionAttrib (hModule, 0, CSL_EDMA3_MEMACCESS_UX |
CSL_EDMA3_MEMACCESS_UW |
CSL_EDMA3_MEMACCESS_UR |
CSL_EDMA3_MEMACCESS_SX |
CSL_EDMA3_MEMACCESS_SW |
CSL_EDMA3_MEMACCESS_SR |
CSL_EDMA3_MEMACCESS_AID0 |
CSL_EDMA3_MEMACCESS_AID1 |
CSL_EDMA3_MEMACCESS_AID2 |
CSL_EDMA3_MEMACCESS_AID3 |
CSL_EDMA3_MEMACCESS_AID4 |
CSL_EDMA3_MEMACCESS_AID5 |
CSL_EDMA3_MEMACCESS_EXT);
*/
//#define USE_PRINTS
#ifdef USE_PRINTS
printf ("*************** Configuration Info (%d) ************\n",edmaObj.instNum);
printf ("Registers address: 0x%08X\n",edmaObj.regs);
printf ("Number Of DMA channels: %d\n",edmaObj.cfgInfo.numDMAChannel);
printf ("Number Of QDMA channels: %d\n",edmaObj.cfgInfo.numQDMAChannel);
printf ("Number Of interrupt channels: %d\n",edmaObj.cfgInfo.numINTChannel);
printf ("Number Of available PaRAM set entries: %d\n",edmaObj.cfgInfo.numParamsets);
printf ("Number Of event queues: %d\n",edmaObj.cfgInfo.numEvque);
printf ("Number Of shadow regions: %d\n",edmaObj.cfgInfo.numRegions);
printf ("Is channel mapping: %d\n",edmaObj.cfgInfo.IsChannelMapping);
printf ("Is memory protection: %d\n",edmaObj.cfgInfo.IsMemoryProtection);
printf ("**************************************************\n");
#endif
//#define DMA_CHANNELS_ENABLE_ACCESS
#ifdef DMA_CHANNELS_ENABLE_ACCESS
/* Enable access for all DMA channels (64 channels) to the SHADOW Region 0. */
regionAccess.region = CSL_EDMA3_REGION_0;
regionAccess.drae = 0xFFFFFFFF;
regionAccess.draeh = 0xFFFFFFFF;
if (CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_DMAREGION_ENABLE, ®ionAccess) != CSL_SOK)
{
printf ("Error: EDMA region enable command failed\n");
return -1;
}
#endif
#define QDMA_CHANNELS_ENABLE_ACCESS
#ifdef QDMA_CHANNELS_ENABLE_ACCESS
/* Enable access to shadow region 0 by our QDMA channel */
/* Write to QDMA region access enable register (QRAE)
* This is done by setting bit0 (corresponds to our QDMA channel 0) in enabling register of shadow region 0 : QRAE0(0) = 1
*/
qraeSetup.region = CSL_EDMA3_REGION_0; // region #0
qraeSetup.qrae = ((Uint32)1)<<QDMA_CHANNEL_USED;
if (CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_QDMAREGION_ENABLE, &qraeSetup) != CSL_SOK)
{
printf ("Error: EDMA QDMA region enable command failed\n");
return -1;
}
#endif
/* QDMA Channel 0 Open
* Upadte the channelObj fields,
* No writing to HW
*/
channelAttr.regionNum = CSL_EDMA3_REGION_0;
channelAttr.chaNum = QDMA_CHANNEL_TO_DMA_CHANNEL(QDMA_CHANNEL_USED);
hChannel = CSL_edma3ChannelOpen(&channelObj, CSL_EDMA3_CC, &channelAttr, &status);
if ((hChannel == NULL) || (status != CSL_SOK))
{
printf ("Error: EDMA channel open failed\n");
return -1;
}
/* Map QDMA Channel to Params Block 0
* * Writing the PAENTRY to the QCHMAPn register
* */
CSL_edma3MapQDMAChannelToParamBlock(hModule, QDMA_CHANNEL_USED, 0);
/*
status = CSL_edma3HwChannelSetupParam (hChannel, PARAMSET_USED);
if (status != CSL_SOK)
{
printf ("Error: Map channel to PaRAMs set entry %d failed\n",PARAMSET_USED);
return -1;
}
status = CSL_edma3GetHwChannelSetupParam(hChannel, ¶mSetNum);
if ((status != CSL_SOK) || (paramSetNum != PARAMSET_USED))
{
printf ("Error: Map channel to PaRAMs set entry %d failed\n",PARAMSET_USED);
return -1;
}
*/
/* Setup the trigger word for the QDMA Channel,
* Writing the TR WORD to the QCHMAPn register
* when we write to the CCNT word the QDMA will start
* */
CSL_edma3SetQDMATriggerWord(hModule, QDMA_CHANNEL_USED, CSL_EDMA3_TRIGWORD_CCNT);
/*
status = CSL_edma3HwChannelSetupTriggerWord(hChannel, CSL_EDMA3_TRIGWORD_CCNT);
if (status != CSL_SOK)
{
printf ("Error: Setup the trigger word for the QDMA failed\n");
return -1;
}
status = CSL_edma3GetHwChannelSetupTriggerWord (hChannel, &triggerWord);
if ((status != CSL_SOK) || (triggerWord != CSL_EDMA3_TRIGWORD_CCNT))
{
printf ("Error: Writing the TR WORD %d to the QCHMAPn register failed\n",CSL_EDMA3_TRIGWORD_CCNT);
return -1;
}
*/
/* Get the handle for the PARAM-SET entry 0 */
hParamPing = CSL_edma3GetParamHandle(hChannel, PARAMSET_USED, &status);
if ((hParamPing == NULL) || (status != CSL_SOK))
{
printf ("Error: EDMA get handle for PaRAMs set entry %d failed\n",PARAMSET_USED);
return -1;
}
/* Setup params */
myParamSetup.option = CSL_EDMA3_OPT_MAKE(CSL_EDMA3_ITCCH_DIS, \
CSL_EDMA3_TCCH_DIS, \
CSL_EDMA3_ITCINT_DIS, \
CSL_EDMA3_TCINT_EN /* Transfer completed interrupt enable */ ,\
0 /* TCC value for checking the IPR(TCC) bit for transfer completed */,\
CSL_EDMA3_TCC_NORMAL,\
CSL_EDMA3_FIFOWIDTH_NONE, \
CSL_EDMA3_STATIC_EN, \
CSL_EDMA3_SYNC_A, \
CSL_EDMA3_ADDRMODE_INCR, \
CSL_EDMA3_ADDRMODE_INCR);
myParamSetup.srcAddr = (Uint32)srcBuff1;
myParamSetup.aCntbCnt = CSL_EDMA3_CNT_MAKE(256,1);
myParamSetup.dstAddr = (Uint32)dstBuff1;
myParamSetup.srcDstBidx = CSL_EDMA3_BIDX_MAKE(0,0);
myParamSetup.linkBcntrld= CSL_EDMA3_LINKBCNTRLD_MAKE(CSL_EDMA3_LINK_NULL,0);
myParamSetup.srcDstCidx = CSL_EDMA3_CIDX_MAKE(0,0);
myParamSetup.cCnt = 1;
/* download the params to the PARAM-SET entry 0. */
if (CSL_edma3ParamSetup(hParamPing, &myParamSetup) != CSL_SOK)
{
printf ("Error: EDMA param setup failed\n");
return -1;
}
/* Enable Channel - Writes to the QDMA event enable register QEER */
if (CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_ENABLE, NULL) != CSL_SOK)
{
printf ("Error: EDMA channel enable command failed\n");
return -1;
}
/* Trigger the word by writing to the trigger word... */
if (CSL_edma3ParamWriteWord(hParamPing,CSL_EDMA3_TRIGWORD_CCNT,1) != CSL_SOK)
{
printf ("Error: EDMA param write word failed\n");
return -1;
}
status = CSL_edma3GetHwChannelStatus(hChannel, CSL_EDMA3_QUERY_CHANNEL_STATUS, &isQer);
/* Poll IPR bit, the TCC value is 0 so we wait for the interrupt with IPR(0) - value 1 */
regionIntr.region = CSL_EDMA3_REGION_0;
do {
CSL_edma3GetHwStatus(hModule,CSL_EDMA3_QUERY_INTRPEND,®ionIntr);
} while (!(regionIntr.intr & 0x1));
/* Clear pending interrupt */
if (CSL_edma3HwControl(hModule,CSL_EDMA3_CMD_INTRPEND_CLEAR, ®ionIntr) != CSL_SOK)
{
printf ("Error: EDMA clear interrupt pend command failed\n");
return -1;
}
/* Check transfer by comparing the source and destination buffers */
if(Verify_Transfer( 256, 1, 1, 0, 0, 0, 0, srcBuff1, dstBuff1,TRUE) == FALSE)
{
printf ("Error: Verification (Source1/Destination1) Failed\n");
return -1;
}
/* Disable the channel */
CSL_edma3HwChannelControl(hChannel,CSL_EDMA3_CMD_CHANNEL_DISABLE, NULL);
/* Close channel */
if (CSL_edma3ChannelClose(hChannel) != CSL_SOK)
{
printf("Error: EDMA channel close failed\n");
return -1;
}
/* Close EDMA module */
if (CSL_edma3Close(hModule) != CSL_SOK)
{
printf("Error: EDMA module close failed\n");
return -1;
}
/* Test Passed. */
return 0;
}
