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PCIe bit error rate mesurement for K2H

UNA
Mastermind 7980 points
Other Parts Discussed in Thread: 66AK2H12

Hi,

I would like to do the measurement of PCIe bit error rate of between 66AK2H12 and FPGA.
I have to consider the procedure, so i'm interested in PBRS.

KeyStone II Architecture Serializer/Deserializer(SPRUHO3B)
[19.1 PRBS Generator and Checker](p184)

Do you know the documents and Wiki information that has been described more detailed for PBRS?


Best regads,
H.U

  • 0
    TI__Guru* 81335 points

    The PBRS tests can be done on all K2 SERDES lanes. There's a lane tuning tool in ti\pdk_keystone2_3_0x_0x_0x\packages\ti\diag\serdes_diag.

    Thank you.

  • 0 in reply to Raja
    Mastermind 7980 points
    Hi, Raja

    Thank you for your reply.
    Please forgive the additional questions.

    I think serdes_diag tool is the approach that should be using two K2 devices.
    I want to measure on our custom board that using K2H(EP) and FPGA(RC).
    Can I use the serdes_diag tool at the our board?

    Do you know registers that it determines whether the bit error has occurred or corrected?
    If it is possible to use such a register, I believe it can be confirmed to increase or decrease the bit error by the registers value amount of change per unit time.

    Best regards,
    H.U
  • 0 in reply to UNA
    TI__Guru* 95265 points

    The Serdes_Diag tool is used for testing between 2 Keystone II device on DSP cores, using CCS/DSS script as a control. For the K2H and FPGA stucture you have to customize your own tool for this.

    The tool reads out the bit error counter on a given measurement time frame at the PCIE Serdes level .

    If you want to see any error happened on PCIE protocol level, you can check those registers: see section 2.16 Error Handling of PCIE user guide.

    Regards, Eric

  • 0 in reply to lding
    Mastermind 7980 points

    Hi, Eric

    Data link layer would have carried out automatically the detection and correction of incorrect data.
    Please tell me if you know the register to display the above status(incorrect data detect and/or correct).

    Best regards,
    H.U

  • 0 in reply to UNA
    TI__Guru* 95265 points
    Look at PCIE_UNCERR bit 4 and PCIE_CERR bit 7.

    Regards, Eric
  • 0 in reply to lding
    Mastermind 7980 points
    Hi, Eric

    Thank you for your reply.

    I understand that approximate bit error rate of PCIe can be measured by cheking PCIE_UNCERR(4bit) and PCIE_CERR(7bit) amount of change per unit time.
    In other words, the bit error rate is high if number of times that these registers are changed is large.

    Is my understanding correct?

    Best regards,
    H.U
  • 0 in reply to UNA
    TI__Guru* 95265 points
    Yes, your understanding is correct. Note those are error bit, not error counter. Which means, when an error occurs, the bit gets set, you need write "1" to clear it.

    Regards, Eric
  • 0 in reply to lding
    Mastermind 7980 points
    Eric

    Sorry for the late reply.
    I understood it.

    Best regards,
    H.U
  • 0 in reply to lding
    Mastermind 7980 points
    Hi, Eric

    I checked PCIE_UNCERR(4bit) and PCIE_CERR(7bit) for the measurement of PCIe bit error rate, but these bits have not been set.
    However, PCIE_CERR.ADV_NFERR_ST bit is sometimes set.

    Please tell me the conditions that PCIE_CERR.ADV_NFERR_ST bit is set.

    Best regards,
    H.U
  • 0 in reply to UNA
    Mastermind 7980 points

    Hi, Eric

    We need your support. Please get back to us as soon as possible.

    Best regards,
    H.U

  • 0 in reply to UNA
    TI__Guru* 95265 points

    H.U,

    I missed your recent post as the previous activity was 2 months away, sorry! It would be good to open a new one in case of long inactivity.

    You can look at PCI Express Base Specification, section 6.2.3.2.4. Advisory Non-Fatal Error Cases: In some cases the detector of a non-fatal error is not the most appropriate agent to determine whether the error is recoverable or not, or if it even needs any recovery action at all. For example, if software attempts to perform a configuration read from a non-existent device or Function, the resulting UR Status in the Completion will signal the error to software, and software does not need for the Completer in addition to signal the error by sending an ERR_NONFATAL Message. In fact, on some platforms, signaling the error with ERR_NONFATAL results in a System Error, which breaks normal software probing.

    So, it looks some non-fatal errors detected, but the detecting agent doesn't know how to handle it, it sends this advisory to SW.

    Regards, Eric

  • 0 in reply to lding
    Mastermind 7980 points

    Hi, Eric

    Thank you for your reply.
    I will check the PCIe specification.

    Best regards,
    H.U