• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 592 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM335X MCASP receive in master mode with clocks derived from transmit part ?

Christoph Apel
Intellectual 540 points

Hello TI support team, hello Biser,

a customer would like us to run MCASP0 receive part synchronously to transmit part.

Transmit part is clocked externally from MCASP0_AHCLKX.

Receive part should provide the clocks in master mode to a DSP. This is the tricky part, because the hardware is already done so they cannot just connect input and output clocks together.

Unfortunately, MCASP0_AHCLKR is not connected...

Question is, if we can configure MCASP0_ACLKR and MCASP0_FSR to output clocks derived from MCASP0_AHCLKX and if yes, how.

thanks a lot and best regards,

Christoph

  • 0
    TI__Guru**** 393215 points
    Hi Cristoph,

    I think this can be achieved by clearing the ASYNC bit in the ACLKXCTL Register (AM335X TRM Rev. M section 22.3.1.28).
  • 0 in reply to Biser Gatchev-XID
    Prodigy 200 points

    Dear Biser,

    we've tried ASYNC = 0, but there is no clock output on neither ASFR nor AHCLKR pin. According to spruh73l.pdf (page 4593, section 22.3.12.5) this scenario is not supported:
    When ASYNC = 0, the receive frame sync generator is internally disabled. If the AFSX pin is configured
    as an output, it serves as the frame sync signal for both transmit and receive. The AFSR pin should not be
    used because the transmit frame sync generator output, which is used by both the transmitter and the
    receiver when ASYNC = 0, is not propagated to the AFSR pin (Figure 22-19).

    Do you have any other idea?

    Best reards,

    Emil

  • 0 in reply to Biser Gatchev-XID
    Intellectual 540 points

    Hi Biser,

    it seems it does not work. We re-checked TRM and found a note which seems to confirm this:

    quote

    When ASYNC = 0, the receive frame sync generator is internally disabled. If the AFSX pin is configured
    as an output, it serves as the frame sync signal for both transmit and receive. The AFSR pin should not be
    used because the transmit frame sync generator output, which is used by both the transmitter and the
    receiver when ASYNC = 0, is not propagated to the AFSR pin (Figure 22-19)

    unquote

    or are we missing anything ?

    thanks and regards, Christoph

  • 0 in reply to Christoph Apel
    TI__Guru**** 393215 points
    Oh, yes, sorry I missed this. I don't see what can be done in this case, except hardware rework.