EDMA3 transfer complete interrupts for region 1 is not generated

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Hi,

Thanks for your post.

Kindly ensure that you didn't enable every channels on all shadow regions because this could cause problem that one transfer completion will generate the interrupts to all the shadow regions. So, it is recommended not to overlap the channel allocation and transfer completion code among the shadow regions.

Usually, EDMA CC would detect a interrupt transfer completion code which is equal to the TCC bit in OPT for the PaRAM entry associated with the DMA channels then the corresponding bit would be set in the interrupt pending register (IPR, IPRH) associated with the channel. For more info. please refer section 4.2.7.4 from the EDMA user guide above.

Please refer to the A.2 Miscellaneous Programming in the EDMA user guide below:

http://www.ti.com/lit/ug/sprugs5b/sprugs5b.pdf

As well, the below E2E post would address your issue since there are scenarios explains when enabled in different shadow regions and generate the shadow region interrupt based on the completion of transfer which would definitely help you:

https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/216073

https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/298397

Thanks & regards,

Sivaraj K

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Hi Sivaraj, thank you for the fat response,

Kindly ensure that you didn't enable every channels on all shadow regions

First of all I could not understand what is enabling a channel on a shadow region. Is this related with DRAE registers,

I am callng below functions in the fallowing order;

1-EDMA3_DRV_Create for 3 instances

2- EDMA3_DRV_Open for 3 instances, (region = coreNum, sampleInstInitConfig[InstId][coreNum] is used)

3 - registerEDMA3Interrupts for 3 instances 

4 - EDMA3_DRV_requestChannel for 2+4+4=10 channels TCC_ANY and DMA_CHANNNEL_ANY is used.

5- Set parameters ans initiate the transfer.

6 -transfer comleted but no interrupt generated. for region IER = 0xC and IPR=0x4 but no interrupt.

For the above trial ChannelID = TCC = 2 is used.  EDMA3_DRV_requestChannel function determined this value.

For a other trial I used region = 0 and sampleInstInitConfig[InstId][0] instead of sampleInstInitConfig[InstId][coreNum]

-The result ChannelID = TCC = 0 but no change for interrupt. (IER = 0x3 and IPR = 0x1)

Not to overlap anything I tried not to use any core except core1. Only core1 is used and the transfer isdone but no interrup is generated. I tried above trial with this configuration.

Is this related with DRAE registers. I tried to enable all bits for used region.

Is this related withevent combiner, becouse when i try the same code n core0 event with eventId 62 and 63 are set to tci interrupts. Ican see this from ROV. When i used core1 no event is set.

Thank you for helping,

Burak

 

Hi,

Did you check the E2E post shared on the scenarios for channels enabled in different shadow regions and generate the shadow region interrupt based on the completion of transfer which clarifies that there shouldn't be any overlap in the channel allocation but allocate the dedicated channel(s) to each CorePac's (shadow region). This is what the statement "enabling a channel on a shadow region" intends to explain. Kindly check the below E2E posts to refer:

https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/216073

Thanks & regards,

Sivaraj K

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Hi Saviraj,
I had read the post but could not had solved the problem, but not now I have managed to solve the problem. It was all my fault. and the problem was related with enabling channels in different regions as you mentioned.

I will click to the verify answer button but I have one more question. Is there any way to check if a transfer is finished or not from another core than the core that initiates the transfer and is interrupted. If i understand correctly, different channelIDs and TCCs in different shadow regions can refer to the same TC in global. So I want to know if the channel is busy and so select another channel to transfer data. Is this a wrong strategy to utilize channels?

Thanks,

Burak

Maybe, I need to explain myself correctly.

I am coding a DMA library and developing an abstraction layer above EDMA driver code. In the library all the transfers will be initiated manually. The user will use the library like memcpy. He can choose waiting or not waiting for the end of transfer. At first all of the 10 channels are requested from all cores. and all core have a shadow region to control the channels.

Now, with the library, A user can copy data. In the code I can choose any channel from totally 10 channels. As I know there is totally 10 TC that transfer data. For each transfer I choose a TC and set the params with inputs that user entered, trigger TC and wait for the interrupt. I have managed to use all TC's from all cores. In one core when two transfer are requested at the same time one can be done by TC0 and the other can be done by TC1. In the code I am looking for a free channel from 10 and start from TC0. If TC0 is busy I should know it. In one core I am looking for a flag that I set after transfer is initiated and reset after the interrupt is generated.

In one core situation the scenario works well but for multicore usage I can not use a simple flag for TCs. I tried to use ESR bit. I read the ESR bit from shadow regs and if ESR bit is set then I think the channel is busy. Actually it worked but not exactly the same with my expectation. All the channels used three times. If we give number to TCs [0-9], the transfers are done with below TCs

[C66xx_0] Used Channels : 0 0 1 2 2 3 4 4
[C66xx_1] Used Channels : 0 1 1 2 3 3 4 5

Note: In the test code two cores want to transfer another data without waiting the previous ones finished. The library chooses channel. It starts from 0 and is it is busy it looks for 1 and continues like that.

If I run the same code in one core. If there is no flag that I set and reset manually, and if the only clue to decide a channel is busy is ESR bit, the core wors like below.

[C66xx_0] Used Channels : 0 0 0 1 1 1 2 2 2 3 3 3

So is there no way to check a channel is busy or not. And when I check the ESR bit why it is set after using three times?

Regards,

Burak