Hi
We are having problem with custom board C6748 Silicon Revision 2.0 "Nor Flash boot" with aisgen binary image.
After unsuccessful boot, the diagnostic gel shows "invalid aisgen sync opcode", with code partially residing on the memory. PSC, PLL and DDR settings are OK.
After a lot of inspection , I may only suspect aisparse copy count gets corrupted while copying the code from flash to internal memory, therefore parser believes a code part is a sync code.
My questions are as follows:
1 ) Is there a way to manipulate PC to debug boot process with CCS? (change PC to start of bootloader program etc)
Do we have the source of ROM bootloader (in assembly or C) which may be loaded as symbols to bootloader?
2) Can I stall the bootloader to be continued after I connect to the DSP via JTAG?
3) Is there any unwritten restriction regarding NOR Flash Bootloader ( unallowed internal memory addresses etc)
Please advise, we are having hard time with project schedules and require dire assistance. I may share the binary image with you via PM if required. Thanks