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Emulation failure on OMAP-L138-EP with 25 MHz input clock

Todd Anderson78572
Guru 14640 points
Other Parts Discussed in Thread: OMAP-L138

All:

We have a target board with OMAP-L138-EP running with a 25 MHz input clock.

I have adjusted the OMAP-L138_LCDK.gel file to create a 300 MHz system clock, 150 MHz DDR clock, and 100 MHz EMIFA clock. When I try to connect to the target, I get the following info displayed:

-----------------------------------------------------------------------------------------------------------

ARM9_0: Output:  Target Connected.
ARM9_0: Output:  ---------------------------------------------
ARM9_0: Output:  Memory Map Cleared.
ARM9_0: Output:  ---------------------------------------------
ARM9_0: Output:  Memory Map Setup Complete.
ARM9_0: Output:  ---------------------------------------------
ARM9_0: Output:  PSC Enable Complete.
ARM9_0: Output:  ---------------------------------------------
ARM9_0: Output:  PLL0 init done for Core:337.5 MHz, EMIFA:112.5 MHz
ARM9_0: Output:  DDR initialization is in progress....
ARM9_0: Output:  PLL1 init done for DDR:150MHz
ARM9_0: Output:  Using DDR2 settings
ARM9_0: Output:  DDR2 init for 150 MHz is done
ARM9_0: Output:  ---------------------------------------------
ARM9_0: Output:  DSP Wake Complete.
ARM9_0: Output:  ---------------------------------------------
ARM9_0: File Loader: Verification failed: Values at address 0x0000000080000000 do not match Please verify target memory and memory map.
ARM9_0: GEL: File: C:\source\FAB_test_ARM_ubootloader\Debug\FAB_test_ARM_ubootloader.out: a data verification error occurred, file load failed.
ARM9_0: Unable to terminate memory download: NULL buffer pointer at 0x320

----------------------------------------------------------------------------------------------------

However, if we use 20 MHz as an input clock, and I adjust the gel parameters for that, everything appears to work.

Any ideas of why I am getting the above error?  I can provide the gel file if necessary.

 

  • 0
    Guru 14640 points
    PLL0 init done for Core:337.5 MHz, EMIFA:112.5 MHz
    Should actually read 300 MHz, EMIFA: 100 MHz. (Sorry, did not update the comment output...)
  • 0
    TI__Guru** 116100 points

    Dear Todd Anderson,


    ARM9_0: File Loader: Verification failed: Values at address 0x0000000080000000 do not match Please verify target memory and memory map.
    ARM9_0: GEL: File: C:\source\FAB_test_ARM_ubootloader\Debug\FAB_test_ARM_ubootloader.out: a data verification error occurred, file load failed.

    I hope you have to modify the DDR timing parameters in gel file (as per your DDR data sheet)
    Please refer to tis wiki page for calculating the DDR2/mDDR timing parameters.



    You can run this example "FAB_test_ARM_ubootloader.out" if you configured for DDR memory.

  • 0
    TI__Guru** 116100 points
    Dear Todd Anderson,
    Can you please attach your gel file ?


    However, if we use 20 MHz as an input clock, and I adjust the gel parameters for that, everything appears to work.

    What is your reference clock ?
    Clock mode ?
    Are you using crystal clock or external oscillator ?
    Have you set correctly the CLKMODE ?

    device_PLL0(unsigned int CLKMODE, unsigned int PLLM, unsigned int POSTDIV,unsigned int PLLDIV1, unsigned int PLLDIV2, unsigned int PLLDIV3, unsigned int PLLDIV7 )

    I can calculate for you if you provide the reference clock used on your custom board.
  • 0 in reply to Titusrathinaraj Stalin
    Guru 14640 points

    OnTargetConnect( )

    {

       GEL_TextOut("\tTarget Connected.\n","Output",1,1,1);

       GEL_TextOut("\t---------------------------------------------\n","Output",1,1,1);

       Clear_Memory_Map();

       Setup_Memory_Map();

       PSC_All_On();

    //    Core_300MHz_mDDR_150MHz(); // original LCDK

    //    Core_337MHz_mDDR_150MHz(); // modified for external 25 MHz clock

     

    //  This was for 20 MHz external clock.    

       Core_300MHz_mDDR_150MHz_E();

       Wake_DSP();

    }

    ...

    Set_Core_337MHz()
    {
     device_PLL0(1,23,1,0,1,3,5); /* was 1,26,1,0,0,2,5 for 25 MHz. */
     GEL_TextOut("\tPLL0 init done for Core:337.5 MHz, EMIFA:112.5 MHz\n","Output",1,1,1);
    }

    Set_Core_300MHz_E()
    {
        device_PLL0(1,29,1,0,1,3,5); /* Changed 11 to 3 */
        GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:100MHz\n","Output",1,1,1);
    }

    Set_Core_300MHz() {
        device_PLL0(0,24,1,0,1,3,5); /* Changed 11 to 3 */
        GEL_TextOut("\tPLL0 init done for Core:300MHz, EMIFA:100MHz\n","Output",1,1,1);
    }

    I have noticed a few differences between the original Set_Core_300MHz() and the newer function. I will try to see if making changes to match these 2 functions more closely will allow for a connection.

    I am also making changes to the  PSC_All_On() function to comment out OMAP features that are NOT being used on our target. Hopefully, these changes will help.

     

  • 0 in reply to Todd Anderson78572
    TI__Guru** 116100 points

    Thanks Todd, this info is sufficient.
    I presume that you are using mobile DDR (LPDDR) and external oscillator is 20MHz always.

    Please make sure that you have followed the recommendations in OMAPL138-EP data sheet, section 5.5 "Crystal Oscillator or External Clock Input" and clock is proper without any jitter.


    Set_Core_337MHz()
    {
    device_PLL0(1,23,1,0,1,3,5); /* was 1,26,1,0,0,2,5 for 25 MHz. */
    GEL_TextOut("\tPLL0 init done for Core:337.5 MHz, EMIFA:112.5 MHz\n","Output",1,1,1);
    }

    For this function, you have to get the same 300MHz only for 25Mhz reference clock.

    I will also ask HW guy to check this problem.

  • 0 in reply to Todd Anderson78572
    TI__Guru** 116100 points

    ARM9_0: Output: ---------------------------------------------
    ARM9_0: File Loader: Verification failed: Values at address 0x0000000080000000 do not match Please verify target memory and memory map.
    ARM9_0: GEL: File: C:\source\FAB_test_ARM_ubootloader\Debug\FAB_test_ARM_ubootloader.out: a data verification error occurred, file load failed.
    ARM9_0: Unable to terminate memory download: NULL buffer pointer at 0x320

    Which memory have you used for generating this "FAB_test_ARM_ubootloader.out" ?
    DDR ?
    If DDR used, can you please to modify the section to internal shared RAM (L3) and check you are getting the same error for 25MHz?

    Have you modified the DDR2/mDDR timing parameter from programming DDR wiki ?
  • 0 in reply to Titusrathinaraj Stalin
    Guru 14640 points
    Arm is being loaded into ONCHIP RAM starting at 0x80000000. (From the ARM map file)
  • 0 in reply to Todd Anderson78572
    Guru 14640 points

    device_PLL0(1,23,1,0,1,3,5); // As I understand the gel file, this is what this gives me:

                           1 = CLKMODE = external clock

                              23 = PLLM  (PLL multiplier) [effectively multiply x 24 --> 600 MHz ]

                                  1 = POSTDIV (Divide by 2) [25 MHz input / 2 = 300 MHz SysClk]

                                     0 = DIV1 [gives value of 1]

                                        1 = DIV2

                                            3 = DIV3

                                                5 = DIV7

  • 0 in reply to Todd Anderson78572
    Guru 14640 points

    All:

    It looks like I am now able to run the processor at 50 MHz input clock frequency.

    The settings for the PLL0 and PLL1 needed to be done correctly.

    Presently, I have a 50 MHz input clock (not oscillator) and my device_PLL0(1,5,0,0,1,3,5) works for setup of CCS. (300 MHz system clock)

    I have device_PLL1(5,0,0,1,2)  set up as well, so that the DDR speed is 150 MHz.

    I am presently working on just what peripherals need to be included (a lot less than the LCDK has enabled).

     

  • 0 in reply to Todd Anderson78572
    TI__Mastermind 43660 points
    Todd,

    If you are using internal oscillator and providing input clock using crystal, the input frequency range is 12 to 30 MHz only. Please refer Table 6-2 in device data manual.

    We would recommend you to adhere to the clock requirements for proper operation of the device.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Guru 14640 points
    We are not using an external crystal. We are using an external 50 MHz clock. Based on the OMAP-L138-EP spec and the PLL's, there is no real gain to using 50 MHz, but it is being used elsewhere in the circuit. It looks like the ideal clock would be a multiple of 15 MHz, because that is the only value that will get you to the 345 MHz maximum frequency. We will be able to reach 337.5 MHz with the 50 MHz input CLOCK.
    Thanks.
  • 0 in reply to Todd Anderson78572
    Guru 14640 points

    "Presently, I have a 50 MHz input clock (not oscillator) and my device_PLL0(1,5,0,0,1,3,5) works for setup of CCS. (300 MHz system clock)

    I have device_PLL1(5,0,0,1,2)  set up as well, so that the DDR speed is 150 MHz."

    The only caveat on this was a change to one parameter in the PLL1, now device_PLL(5,0,0,1,3). The DIV3 parameter was changed from 2 to 3 because of a "red line" in the Excel spreadsheet (SYS_CLK_CALC_OMAP-L138_C674X_AM18X_v1p3.xls).