DM6446 SPI Boot configrations

UNA

Hi,

I would like to try spi boot by DM6446(Sillicon rev 2.3),
but it seems that your documents does not discrived SPI clock speed, polarity and phase at SPI boot mode.
Do you know SPI configuration and PLL setteing at SPI boot mode?

Best regards,
H.U

over 10 years ago

0 Sivaraj Kuppuraj over 10 years ago

TI__Mastermind 35645 points

Hi,

We will work on this and will address your request shortly.

Thanks & regards,
Sivaraj K

0 UNA over 10 years ago in reply to Sivaraj Kuppuraj

Mastermind 7980 points

Hi, Sivaraj

Any update on this?

I'm looking forward to reply from you.

Best regards,
H.U

0 Titusrathinaraj Stalin over 10 years ago

TI__Guru** 116100 points

Sorry for the delayed response on this.
I'm checking with internal team on this.

~\DM644x_FlashAndBootUtils_2_00\DM644x\Common\src
~\DM644x_FlashAndBootUtils_2_00\Common\ubl\src

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

H.U,

I think the SPI configurations foe the SPI boot is not explicitly available in the document. You may need to refer the boot source code to get these information. Please refer the source code links provided by Titus.

Regards,
Senthil

0 UNA over 10 years ago in reply to Senthilkumar Srinivasan

Mastermind 7980 points

Hi, Senthil

I am confused by your comment.
Are you say that the source code links is "DM644x_FlashAndBootUtils_2_00" ?

I want to know SPI and PLL configurations by ROM boot loader,
but DM644x_FlashAndBootUtils_2_00 tool is not include the ROM boot loader code.

So, Could you provide a link for ROM source code?

Best regards,
H.U

0 Titusrathinaraj Stalin over 10 years ago in reply to UNA

TI__Guru** 116100 points

Hi,
We won't share the RBL code to customers, I'm checking with internal team, they will refer the ROM code and will update here.
Thanks for your patience.

0 UNA over 10 years ago in reply to Titusrathinaraj Stalin

Mastermind 7980 points

Hi,

Can you tell me about the progress on this?
Please give me an answer as soon as possible.

Best regards,
H.U

0 UNA over 10 years ago in reply to UNA

Mastermind 7980 points

Hi, Titus

Please excuse this reminder.
My customer is waiting for the information from you.

Best regards,
H.U

0 Titusrathinaraj Stalin over 10 years ago in reply to UNA

TI__Guru** 116100 points

Sorry for the delay in responding.
Actually I have requested the factory team for that.
I'm following up with them.

Thanks for your patience.

0 Titusrathinaraj Stalin over 10 years ago in reply to UNA

TI__Guru** 116100 points

I have got the ROM source code today, here is the required information.

Do you know SPI configuration and PLL setteing at SPI boot mode?

The following comments from RBL code and it tells about the SPI configuration in ROM boot.
In RBL, the PLL is in bypass mode. i.e it runs at reference clock.

/* for VBUS CLK = 92/3 MHz */
/*SPI mode (phase = 1, polarity = 0) Shift MSB first, 8 character length and SPICLK = VBUSP CLK/(preScaler+1) */
/* if preScaler = 0 (default) then SPICLK = VBUSP CLK/2 */
/* set the CS high delay time = (WDELAY+2)CLKPeriod = (14+2)CLKperiod = 500ns */

/*CS timing requirements @ VBUS CLK = 92/3 MHz */
/* set CS hold,setup time delays - should be atleast 500ns */
/* set the CS setup delay time = (C2TDELAY+2)CLKPeriod = (14+2)CLKperiod = 500ns */
/* set the CS hold delay time = (T2CDELAY+1)CLKPeriod = (15+1)CLKperiod = 500ns */

Please let me know for further information if any.

Apologize for the delay.

0 UNA over 10 years ago in reply to Titusrathinaraj Stalin

Mastermind 7980 points

Hi Titus,

Thank you for your reply.

I have a few questions.
What is the VBUS CLK(= 92/3 Mhz)? VBUS CLK is SPI Module clock?

I think that SPICLK is calculated by the following formula.

SPICLK = (Reference Clock / 6 ) / (Prescaler + 1)
- SPI module clock is supplied by SYSCLK5(= PLLDIV5(/6)).

Is my thinking correct?

Best regards,
H.U

0 Titusrathinaraj Stalin over 10 years ago in reply to UNA

TI__Guru** 116100 points

You are right, as per SPI UG, the SPI clock is

SPI_CLK frequency = [SYSCLK5 frequency ] / [PRESCALEn + 1]
PRESCALEn is only supported for values >1, where the maximum SPI clock rate is (SYSCLK5)/3.

Have you probed the SPI clock in SPI master boot mode (RBL stage) ?

I think, SYSCLK5 will be "Ref clock/6" as PLL will be in bypass mode in RBL.

Let me ask this to internal team.

0 UNA over 10 years ago in reply to Titusrathinaraj Stalin

Mastermind 7980 points

Hi Titus,

Thank you very mach.

I don't have evaluation board that corresponds to the SPI boot.
so, it will be going to experiment by our customer.

Best regards,
H.U

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DM6446 SPI Boot configrations