• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 99 subscribers
  • Views 827 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Some question of CDCM6208V2RGZT for C6678

bing zhou
Prodigy 130 points
Other Parts Discussed in Thread: CDCM6208

Hi Sir

I have two question for CDCM6208V2RGZT for C6678:

1.I want to CDCM6208V2RGZT can be used in C6678?

2.Our project has a  strange phenomenon, our project has four DSP(DSP0,DSP1,DSP2,DSP3),hyperlink connection Between DSP0,DSP1,another Between DSP0,DSP1, when R797 is on board for OSC1,then memory testing is stable ,but hyperlink testing is not stable between DSP0 and DSP1;

when R797 is NC,hyperlink is stable(speed 10Gpbs),but memory is not stable,Now I don't know how to debug it,please help,thanks very much.

  • 0
    TI__Mastermind 43660 points
    Hello,

    I will check on this and update you.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 130 points
    Hi Senthil
    thank you,I'm waiting for your message！

    Jesse
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 130 points
    Hi Senthil
    Please help to check it and update it,our project is urgent，thank you very much！
    Jesse
  • 0
    TI__Mastermind 42545 points

    Hi,
    The CDCM6208 can be used as a clock generator for the C6678. The behavior you described indicates some kind of clock integrity problem but I can't tell you why changing the resistor changes the behavior. There are a couple of things that you can change to help improve the clock integrity.

    1) The DDR clock frequency you label in the schematic is 66.666MHz on output Y5. This output uses pre-scalar A which is also used by Y0, Y1 and Y4. Y0 uses an integer divider from PS_A to get 100MHz which means that Y5 would have to use a fractional divider of /4.5 or /3.75 to get 66.667MHz. The fractional divider settings have a larger jitter component on the output compared to an integer divider. I suggest you set the DDRCLK to 100MHz using on the integer portion of the divider for Y5 and adjust the PLL settings for the DDR PLL inside the C6678.

    2) For the highest data rates achievable by the Hyperlink interface, it is better to use a reference clock for both C6678 devices that is frequency aligned. The reference clock should be connected to two separate outputs of the same CDCM6208 for the best performance. Ideally, these outputs would come from the same pre-scalar and be generated using an integer divide-down.

    I am confused by the values you have selected in the attached schematic page. I can't figure out how to generate the 100MHz system clock on Y0 and the 312.5MHz on Y2 using the CDCM6208V2. Can you provide the configuration file?
    Regards,
    Bill