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SYSBOOT Resistor Values

ARM arm
Expert 2630 points
Other Parts Discussed in Thread: AM5728, AM3358

Hi,

Can the sysboot resistor values of AM335X series be of the value 220K.

I have 220K in stock at present. It is 100K on BBB.

Regards

  • 0
    TI__Guru**** 393215 points
    Hi,

    You can try for 220k for development, but for production I would suggest you stick to 100k.
  • 0 in reply to Biser Gatchev-XID
    Intellectual 445 points
    Hi Biser,

    is there any recommendation for the SYSBOOT pull values in the documentation?

    Are there differences between different Sitara families (335x, 4xxx, 57xx)?

    I wonder why you recommend 100k vs. 220k. The current EVM for the AM5728 implements 10K pulls.
    For an AM5728 design would you recommend the 10K or increase to 100K?

    Regards

    Wolfram
  • 0 in reply to Wolfram Stumpf
    TI__Guru**** 393215 points
    The SYSBOOT pins on AM335X, AM437X and AM57X devices are HiZ at reset release time, when the SYSBOOT configuration is latched. The idea is to ensure that the signals at these pins have settled to the desired value at reset release time, taking into consideration parasitic capacitances, etc. On different EVMs values from 10k to 100k have been used.
  • 0 in reply to Biser Gatchev-XID
    Expert 2630 points
    Gerald told that TI recommends 52K or something but its already pushed to 100K on BBB.

    Hence I have paralleled 220K to bring it to 110K. It works fine on my h/w.

    Regards
  • 0 in reply to ARM arm
    TI__Guru 63395 points

    The answer to this question is system dependent and needs to be evaluated on a per system, per pin basis.  The voltage applied to the SYSBOOT input must be above the min VIH or below the max VIL when the respective reset input rises above its max VIL.  Each external pull resistor will need to be sized such that it pulls the respective SYSBOOT input to the appropriate level in the time provided by the shortest reset pulse.  You also need to consider the effect of leakage current through all devices attached to each SYSBOOT signal. This includes worst case input leakage of the input buffer plus any leakage through internal resistors.

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 335 points

    Hi Paul, 

    What are the max VIL levels for the Sysboot? I'm at about 1V, and seem to be OK, but don't want to run into trouble if this is marginal. We're running with those at 3.3V. 

  • 0 in reply to Hattie Spetla
    TI__Guru 63395 points

    The VIL max and VIH min levels should be published in the respective device data sheet.

    Which device are you asking about?  Have you looked for these values in the respective data sheet?

    Regards,
    Paul

  • 0 in reply to peaves
    Intellectual 335 points
    AM3358. Do the SYSBOOT fall under "All other LVCMOS pins (VDDSHVx = 3.3 V; x = 1 to 6)?"
    Is startup helped by the hysteresis?
    I'm just surprised my system is working so well considering the 1V VIL on the Sysboot pins.
  • 0 in reply to Hattie Spetla
    TI__Guru 63395 points
    The SYSBOOT[15:0] inputs are applied to the LCD_DATA[15:0] terminals.

    If you search the DC Electrical Characteristics section for the terminal name of interest and do not find it explicitly listed, you should use the data from "All other LVCMOS pins (VDDSHVx = 3.3 V; x = 1 to 6)" if operating the respective VDDSHVx at 3.3 volts, or you use the data from "All other LVCMOS pins (VDDSHVx = 1.8 V; x = 1 to 6)" if operating the respective VDDSHVx at 1.8 volts. In your case the terminal of interest is LCD_DATA and all of the LCD_DATA terminals are powered by VDDSHV6.

    1 volt is near the limit for either use case, so you are just getting lucky. You should try to understand why is it not lower and try to resolve the issue.

    Regards,
    Paul
  • 0 in reply to peaves
    Intellectual 335 points
    I'm usually not that lucky. We've had a pretty good run with this design.
    I've only run into problems when I made an adjustment which *lowered* my VIL (and my VIH.) Some kernel panics and issues with the clock caused by marginal voltage on the VIH. Lead to me take a closer look at the levels overall.

    I'm going to correct this in the design - but
    is it possible the hysteresis is giving a larger margin on startup? Min is 0.265. It's close but it fits.
  • 0 in reply to Hattie Spetla
    TI__Guru 63395 points
    The VIL max published in the data sheet is a conservative value. The actual switching threshold is most likely near VDD/2 which could be considerably higher than 1 volt if you are operating the IO supply at 3.3 volts.

    Regards,
    Paul