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AM335X: EtherCAT configuration as standard TCP/IP

Other Parts Discussed in Thread: AM3359, AM3357

I know that Sitara AM3357BZCZA30 can support EtherCAT. Can one of EtherCAT ports be reconfigured by software as a standard Ethernet port such as TCP/IP or UDP for backwards compatibility?

From "Whit paper" by Maneesh Soni, Systems Manager, ARM® microprocessor group, TI, "Customers are expected to become ETG members (required to market EtherCAT products) and get entitled to obtain a free copy of the Beckhoff stack directly via the ETG website before taking their product to market. A copy of the EtherCAT stack from Beckhoff is also included in the TI Industrial SDK for evaluation, development and test purposes."

When in production withSitara AM3357BZCZA30 , is EtherCAT free of license and royalty free?

Many thanks.

  • I will ask the Industrial team to comment.
  • Hi Bailin,

    Bailin Cao said:
    Can one of EtherCAT ports be reconfigured by software as a standard Ethernet port such as TCP/IP or UDP for backwards compatibility?

    If you use the TI EtherCAT ESC running via PRU-ICSS that is not an option. Our implementation is a two-port device.

    If you do master via CPSW (an option supported by TI 3Ps) then you can try to use one port of the switch for EtherCAT master and the other as standard EMAC. However that is a use case not directly supported by TI software or any tests (at least so far).

    TI does not charge for EtherCAT but restricts the use to special devices (e.g. AM3357 or AM3359). For other legal aspects of EtherCAT please discuss with ETG. We are not allowed to provide the stack source anyway.


    Regards,

  • Hi Frank,

    Thank you for your reply.

    From the physical connections from AM3357 to the EtherCAT PHY chips, it seems to me that the AM3357 physical pins used to connect either of EtherCAT PHYs can be used for a standard EMAC port although their IPs are different. Am I correct?

    Regards,
  • Not sure if I get the question. In AM335x we have pins and signals. Through pin mux pins (or better balls..) can get assigned to signals. They may have totally different functions... some signals such as the PRU-ICSS MII interface require software to make them really work. While theoretically their might be many combinations possible usually available software limits this.
  • From Figure 1-1 on page 5 of AM335X datasheets, there are two EMACs available and PRU-ICSS which includes EtherCAT, PROFINET, EtherNet/IP and others. Can you use pin mux to configure the pins of a standard EMAC as the same as the pins of one of EtherCAT ports if EtherCAT is not required?

  • Yes, there is an additional Gbit switch inside the AM335x. This may be run in switch mode with two external ports or as 2 EMACs. Now the Gbit switch has more flexibility in terms of interfacing to phys as it supports MII, RMII and RGMII modes. Finally, using pin-mux it is possible to overlay some of that with the MIIs provided by PRU-ICSS. However that requires a careful design and can't be answered here in general. You may use the ICEv2 schematics as an example. There we have two RJ45 connectors on the board. Depending on jumper settings (and matching SW loads!) the Ethernet phys are connected to either switch ports or PRU-MII (e.g. for EtherCAT slave). This actually required some additional mux on the board to make it work.

    Another possible pin-mux option is to connect two MII phys to PRU-ICSS and one more to the switch. Again it depends on overall pin-mux evaluation and what other peripherals/interfaces are required.

    Regards,

  • Thank you very much indeed, Frank.

    Is ICEv2 an Eval kit? What is the link to its schematics?

    Regards,

  • Hi Frank,

    I had a quick look at the schematics of ICEv2. It seems to me that those mux chips U7,U8,U9, and U10 are mainly used to switch between MII and RMII or RGMII. If both a standard MAC and EtherCAT are in MII or in RMII or in RGMII, I don't think that physical mux chips are required. In this case, only internal pin-mux is required to switch a standard EMAC to one of EtherCAT ports. Am I correct? Do I understand your answer correctly? 

    Many thanks and kind regards, 

  • As far as i know the overlap between CPSW MII and PRU MII is not 100%. Otherwise I would have expected a simple solution on ICEv2 also. So my answer is no, but you can always use the pin-mux tool and evaluate your dedicated use case.
  • Do you meant that their physical overlap at their ports is not 100%? If not, what is the difference?
  • Bailin,

    A couple of comments:

    1) Regarding the PRU-ICSS:
    Starting with the RTOS SDK 2.00.02 (PROCESSOR-SDK-RTOS-AM335X) we do provide an ICSS-EMAC firmware so that the PRU-ICSS can be used as a standard EMAC:
    http://www.ti.com/tool/PROCESSOR-SDK-AM335X
    This mean that you could have:
    - Ethercat:  Cortex A8 run ethercat slave stack and PRU-ICSS runs the Ethercat salve firmware and interface to PHY via  MII.
    or
    - Ethernet: Cortex A8 run the TI TCP IP stack and PRU-ICSS runs the ICSS-EMAC firmware and interface to PHY via MII.

    In term of SW, to support this, you will need to incorporate the needed portion of the SYSBIOSSDK-IND-SITARA into the PROCESSOR-SDK-RTOS-AM335X.

    Keep in mind that:
       - Only one of the two option will run at a time.
       - The same MII ports and PHY are used.




    2) To have both Ethercat + Ethernet at the same time:

    - You need to use both the PRU-ICSS and the CPSW:
    As far as I know from the 4 on-chip Ethernet ports then 3 Ethernet can be available on the pins at a time due to the pin muxing.
    You can use the cloud based PINMUX tools to see what the valid pinmux combination are:
    https://dev.ti.com/pinmux
    For example you could have the MII0/MII1 of the PRU-ICSS and RMII1 of the CPSW available on different pins with no pin overlap.

    - From the SW point of view:
    In term of SW you still need to incorporate the needed portion SYSBIOSSDK-IND-SITARA into the PROCESSOR-SDK-RTOS-AM335X.
    The difference here is that you use the TI TICP IP stack (NDK) using the CPSW SW driver instead of the ICSS-EMAC.

    Keep in mind that:
       - 3 different MII ports are used (if you choose the pinmux option carefully there should not be any pin collision)
      - In term of Cortex A8 CPU performances it might not be able to run both the Ethercat stack and TI TCP IP stack. You will need to make some benchmarks to check.

    A.

  • If I want to start a design including either Ethernet or EtherCAT (for future expansion) with an AM335X, which AM335X evaluation board can you recommend  to buy and then start with? Thanks.

  • If you are looking at Ethercat (using SYSBIOSSDK-IND-SITARA SW or  SDK RTOS with future Ethercat add-on) or 10/100 Mbit Ethernet (using SDK RTOS) on the PRU-ICSS then you can look at the ICEv2.

    I don't think that the CPSW MII/MDIO is routed on the ICEv2.

    A.

  • Does this discussion also apply to the AM571x devices?

    I am working on a design that needs two real-time EtherCat ports and also a standard Ethernet port? I presume from this discussion that firmware support to run 100Mbit standard Ethernet on the PRU-ICSS is available, such that I can software-configure either two EtherCat ports driven by the PRU-ICSS or one EtherCat and one standard also both driven by the PRU-ICSS.

    I understand that I can use the GMAC peripheral for standard Ethernet, but if I can reduce hardware complexity by running standard Ethernet on the PRU, I would prefer that option.

    Can you please confirm my understanding?

    Thanks,
    Nate
  • Hi Nathan,

    recommendation is to open a new thread for new issues. You may refer to older ones of course.

    Anyway in your case you may use the second PRU-ICSS on AM571x devices as a normal Ethernet MAC or use GMAC. Our PRU-ICSS EtherCAT slave solution always consumes both PRUs in a PRU-ICSS subsystem due to the architecture of the software. It doesn't matter if you use one or two ports in that case.

    Regards,