[AM5728] DPI Video Output frequency

At lower speeds, most interfaces work by having the transmitter launch data on one edge, while the receiver latches it on the opposite edge. In this scenario setup/hold times are centered on the receiving edge. In this scenario you are only using HALF of a cycle from launch to sample.

At higher speeds, the cycle times become too small to meet setup/hold requirements. In this case, most devices use the FULL cycle for timing. In this case, the timings are skewed to no longer be centered on the edge. In this case, the transmitter launches on one edge and the receiver latches on that SAME edge a full cycle later. For this to work, the transmitter's minimum output delay needs to be larger than the receiver's hold requirements.

So that's the background on why we have chosen these timings. Can you please tell me the specific device that won't work with these timings? I wanted to look at the device's data sheet to verify whether or not it might work. Often times I find customers thinking in terms of "half cycle timings" and not understanding to think of the interface in the context of "full cycle timings".

Kaka said:

Please let confirm for understanding of "Default" and "Alternate". I drew the figure of those timings and attached it as below.

No, that's not right.  Your diagram looks like DDR vs SDR.  The difference is whether the launching/sampling occur on the same edge or on opposite edges.

Kaka said:

By the way, would you please teach me the reason why the parameters of D5 and D6 on table 7-15 and table 7-16 are exchanging.

This looks like a copy/paste error.  The "description" column looks right, but it looks like the "Parameter" values were flipped by mistake.  D5 and D6 have the same meaning across both tables.  I'll submit a correction.

Kaka said:

And how customer change the mode of "alternate" from "default"?

This is determined by the Virtual or Manual I/O Mode as listed in Table 7-2 "Modes Summary".

Ok, I drew a picture to try and make this clear:

A few notes on the drawing:

• Everything is based on rising edge in the diagram I drew. In other words, the expectation is that the FPGA is sampling the data on the rising edge, and also that the display port is configured to drive/launch data on the rising edge.
• Looking at the first rising edge you can see that the FPGA would be sampling Data N-1.  On that same edge, the AM572x would launch Data N.
• We specify that there will be a delay from the rising edge of 1.45ns.  I included a little extra margin to account for transition times, so if for example the FPGA hold time requirement is around 1ns, this should be fine.  I think 1.2ns is about the largest hold time that would work as shown in the diagram.
• For the setup time I used the cycle period and subtracted the max output delay time.  That's the longest possible delay specified and so that number will be the worst case for use in computing the needed FPGA setup time.  So as long as the FPGA setup time is less than 1.91ns that timing should work fine.

Brad