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address scheme on CE3 (C6000 -C6713)

Daniel Gaucher
Intellectual 300 points
Other Parts Discussed in Thread: TMS320C6713B

Two quick questions (C6000 - C6713 in particular)

Why is it that the EMIF does not expose address lines A0 and A1 on CE2 and CE3?

Is there a document or a source that explains how the byte enable lines (BE0-3) are used? How the mechanic of those lines works and their purpose.

Thanks

Daniel

U of Sherbrooke

  • 0
    TI__Guru* 84110 points

    Daniel,

    Please refer to the C6713 datasheet and to the EMIF User Guide for more explanation of the EMIF lines. You can find both of these documents by going to the TMS320C6713B Product Folder and then to the Technical Documents tab.

    Regards,
    RandyP

  • 0 in reply to RandyP
    Intellectual 300 points

    Thanks Randy

    I already went through those documents. Still, out of curiosity, I haven't seen an explanation as to why A0 nd A1 are missing on CE3 . Some of my students mignt end up asking that same quesiton. Same for the mechanics and usage for BEx lines. I must admit as you have seen, that I'm not a guru on memory technologies. I may not be missing a lot and a little bit of a hint may help.

    A+

    Daniel

  • 0 in reply to Daniel Gaucher
    TI__Guru* 84110 points
    Daniel,

    Have you signed up for the University Program, yet? TI has a wealth of support files and presentations to help instructors with developing courses based on our DSPs. If you have not, you can find information on it starting from TI.com and the Support & training tab.

    When talking about the address lines, you have to be very precise which labels you use. For example, there is no A0 or A1, nor A2 or A3. There are EAx signals on the EMIF bus. These are shared with CE3 and CE2 and CE1 and CE0.

    We have a C6713 training class archived on our Wiki. The best way I know to find it is to look for the "C6713 workshop" (no quotes) and scroll down for the "TMS320C6x1x DSP Integration Workshop". Strange name but meaningful to the author. It may have some better discussions on the addressing.

    In earlier DSPs, we sometimes numbered the external address lines in different ways. Different designers knew the 'right' way to do it and made it confusing to the rest of us. The first TI processor I used out of college was based on the SBP9989 - it numbered address and data lines from left to right because that is the way you count: A0 was the MSB, D0 was the MSB for data. It got worse from there, and it was not just TI.

    The C6000 devices are more sensible, but that may be because I am used to them.

    The EMIF User Guide shows a lot of information for you, but it is not intended to tell you 'why' something is done only how to use it. I hope it accomplishes that. I would have thought Table 3-1 would do it. There are several Tables that have translations between the TI DSP's address lines and the memory device's address lines, like Table 3-2 showing how to translate between EAx and Ay. Table 3-3 has that for SDRAM, which is even more confusing than Table 3-2. For both of these, the way to use it is to pick the line that matches the device you are using and then use that translation mapping for things to work. Practical is the intention.

    Figure 3-7 might help with BEx a little, but I am not sure if that is what you are looking for. The text in the 3rd paragraph under 3.4.1 tries to add something for the SDRAM case, if that helps.

    Regards,
    RandyP