Other Parts Discussed in Thread: AM3517
We will connect both an FPGA (Xilinx XC6SLX16) and an extra CAN controller (NXP SJA1000 through a level converter) to the GPMC bus on an AM3517. The FPGA is designed with a 16 bit bus and the CAN controller is 8 bit. Question is how should we do the layout? is the GPMC bus a high speed bus which need length matching etc. or a slow local bus with 55ohm to GND?
We have searched for design recommendations without luck. We found high-speed interface layout guidelines (SPRAAR7E) from TI and EDM spec. and design guide (3.13. General Purpose Memory Controller Bus) from a 3rd party. The 3rd party company claim that the GPMC bus is a slow local bus but is that true?
Can anyone come up with a guideline?
If we should follow the 3rd party guideline we should avoid stubs but how do we handle the combination of an eight bit bus and a 16 bit bus?
