Im using a cc1310 cpu with TI RTOS (tirtos_cc13xx_cc26xx_2_15_00_17).
This system is configured to communicate as SPI-Master using SPI driver (SPICC26XXDMA.h).
It works, but between the DMA transactions I have a delay of about 125us. I activated the logger and discovered 4 delay of about 30us.
Line |
rel. Time |
Time |
|||
1 |
0 |
114685058 |
0 |
Cortex_M3_0 |
SPI:(@40000000) DMA transfer enabled |
2 |
0 |
114685058 |
0 |
Cortex_M3_0 |
SPI:(@40000000) DMA transaction: @200037e8, rxBuf: @0; txBuf: @200008f1; Count: 2 |
3 |
30518 |
114715576 |
0 |
Cortex_M3_0 |
SPI:(@40000000) transfer pending on transferComplete semaphore |
4 |
0 |
114715576 |
0 |
Cortex_M3_0 |
SPI:(@40000000) hwi interrupt context start |
5 |
30517 |
114746093 |
0 |
Cortex_M3_0 |
SPI:(@40000000) hwi interrupt context end |
6 |
0 |
114746093 |
0 |
Cortex_M3_0 |
SPI:(@40000000) hwi interrupt context start |
7 |
0 |
114746093 |
0 |
Cortex_M3_0 |
SPI:(@40000000) hwi interrupt context end |
8 |
30518 |
114776611 |
0 |
Cortex_M3_0 |
SPI:(@40000000) swi interrupt context start |
9 |
0 |
114776611 |
0 |
Cortex_M3_0 |
SPI:(@40000000) DMA transaction: @200037e8 complete |
10 |
0 |
114776611 |
0 |
Cortex_M3_0 |
SPI DMA:(@40000000) posting transferComplete semaphore |
11 |
30517 |
114807128 |
0 |
Cortex_M3_0 |
SPI:(@40000000) swi interrupt context end |
Looking at the drivers code, I figured out:
Line 2->3: SSIIntEnable() is called.
Line 10->11: Semaphore_post() is called.
I wonder where those delays are come from?
Regards Armin