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What're Shared Events on the 66AK2H14/12/06

Other Parts Discussed in Thread: 66AK2H14, 66AK2H06, SYSBIOS


The following Figure 6-4 show the 66AK2H14/12 interrupt topologies.CIC2 has 103 event outputs which provides 8 Shared Events to each of the C66x CorePacs, 0 through 7.
I can't fand these on Table 6-22 (the mapping of system events),and host interrupt ID.

  • In table 6-22 look at 24, 25, 99 109

    And here is a screen shot

    Ran

    • question 1:

    For 66AK2H14/12 in figure 6-4,CIC2 provides 8 Shared Events to each of the C66x CorePacs, 0 through 7,
    For 66AK2H06 in figure 6-5,CIC2 provides 4 Shared Events to each of the C66x CorePacs, 0 through 7.
    Therer're only 4 system events in table 6-22,what're others?

    • question 2:

    SRIO block events INTDST0 need to be aggregated through the interrupt controller ( (CIC)) before
    they are routed to the EDMA3CC and C66x Core0. To achieve the requirement,CIC0 (CSL_CIC0_SRIO_INTDST0) ,CIC2 (CSL_CIC2_SRIO_INTDST0) can be used. myDioTxCompletionIsr is called by sysbios when CIC0 is used to map, but myDioTxCompletionIsr can't be triggered when CIC2 is be used. Why?

    CIC0 codes:
    /* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
    CpIntc_dispatchPlug(CSL_CIC0_SRIO_INTDST0, (CpIntc_FuncPtr)myDioTxCompletionIsr, (UArg)hSrioDrv, TRUE);

    /* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 5. */
    CpIntc_mapSysIntToHostInt(0, CSL_CIC0_SRIO_INTDST0, 5);

    /* Enable the Host Interrupt. */
    CpIntc_enableHostInt(0, 5);

    /* Enable the System Interrupt */
    CpIntc_enableSysInt(0, CSL_CIC0_SRIO_INTDST0);

    /* Get the event id associated with the host interrupt. */
    eventId = CpIntc_getEventId(5);

    /* Plug the CPINTC Dispatcher. */
    EventCombiner_dispatchPlug (eventId, CpIntc_dispatch, 5, TRUE);

    CIC2 codes:
    /* Map the System Interrupt i.e. the Interrupt Destination 0 interrupt to the DIO ISR Handler. */
    CpIntc_dispatchPlug(CSL_CIC2_SRIO_INTDST4, (CpIntc_FuncPtr)myDioTxCompletionIsr, (UArg)hSrioDrv, TRUE);

    /* The configuration is for CPINTC0. We map system interrupt 112 to Host Interrupt 8. */
    CpIntc_mapSysIntToHostInt(2, CSL_CIC2_SRIO_INTDST4, 13);

    /* Enable the Host Interrupt. */
    CpIntc_enableHostInt(2, 13);

  • question 1:

    For 66AK2H14/12 in figure 6-4,CIC2 provides 8 Shared Events to each of the C66x CorePacs, 0 through 7,
    For 66AK2H06 in figure 6-5,CIC2 provides 4 Shared Events to each of the C66x CorePacs, 0 through 7.
    Therer're only 4 system events in table 6-22,what're others?

     

    I forward your question to the person who designed the module and here is his response:

    I have only 4 CIC2 events per corepac in the spec. Two are shared across all, each core gets two other unique outputs. So I think that the Figure is wrong. 

    Thank you.