I have a PCIe EndPoint that can successfully write into the DM816X physical memory but cannot read from the PCIe RootComplex.
From the point-of-view of the DM816X. If writing to the DM816X works. Shouldn't reading work as well. Are there any other switch/registers that affect read access.
DM816X is configured as a RootComplex with BAR1 configured as 16MB of prefetcheable memory. My EndPoint is an FPGA with a vendor supplied PCIe core and custom logic on top. DM816X access to the FPGA EndPoint functions correctly for both read and write transactions.
A single 32-bit write initiated from the EndPoint functions correctly - I can correctly read the value from physical memory. I've also tried mapping the inbound translation window to OnChipMemory(OCM) but the results are the same (write is ok, read fails).
When a single 32-bit read is initiated from the EndPoint no completion packet seems to be received by the EndPoint.
A typical write packet from EP to RC : 0x40000001 0x8004000f 0x20000004 0xefbeadde
A typical read-packet from EP to RC : 0x00000001 0x8005010f 0x20000004
Here's some more info:
PCIe Config (lspci)
00:00.0 Class 0604: Device 104c:8888 (rev 01)
Flags: bus master, fast devsel, latency 0
Memory at 21100000 (32-bit, non-prefetchable) [size=4K]
Memory at 20000000 (32-bit, prefetchable) [size=16M]
Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
Memory behind bridge: 21000000-210fffff
Capabilities: [40] Power Management version 3
Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [70] Express Root Port (Slot-), MSI 00
Capabilities: [100] Advanced Error Reporting
01:00.0 Class 0500: Device 10ee:0008
Subsystem: Device 10ee:0008
Flags: bus master, fast devsel, latency 0
Memory at 21000000 (32-bit, non-prefetchable) [size=32K]
Memory at 21008000 (32-bit, non-prefetchable) [size=128]
Capabilities: [40] Power Management version 3
Capabilities: [48] MSI: Enable- Count=1/1 Maskable- 64bit+
Capabilities: [58] Express Endpoint, MSI 00
Capabilities: [c0] <chain broken>
Inbound pcie address configuration:
IB_BAR0 == 1 , IB_START0_LO == 0x20000000 , IB_START0_HI == 0x0 , IB_OFFSET0 == 0x8b000000
Register dump of pcie inbound address translation @51000300
0x51000300 : 0x00000001 0x20000000 0x00000000 0x8B000000
0x51000310 : 0x00000000 0x00000000 0x00000000 0x00000000
0x51000320 : 0x00000000 0x00000000 0x00000000 0x00000000
0x51000330 : 0x00000000 0x00000000 0x00000000 0x00000000
