Champs, I am confused by the AM572x VIP section of the TRM, which is to say I've read it...
So probably the simplest question I can ask is, what is the maximum number of PCLKs between falling edges of HSYNC that the VIP on AM572x can handle (and maybe pursuant to this; what register or TRM section should I have been looking at to have determined this for myself)?
Specifically at this point, just high level; the module states support for things close to 4K..
It says:
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Supports up to 2047 pixels wide input - when scaling is engaged
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Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without scaling
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Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling
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The maximum input resolution support is further limited by pixel clock and feature-dependent constraint
So... it would seem that we can get close to a 4K input; which is what I'm trying to do- specifically 4000 pixels/line. Now that said though; it seems I am close to the limit; but these limits seem to be related ot scaling and chroma subsampling functions; which would only be applicable to the ACTIVE pixels, NOT the blanking, correct? That is, a 4000 pixel wide input; probably has close to 4300 or so actual PCLKs per line; 4000 active ones and maybe 7-10% blanked. I would guess even a 3840 wide input is over 4096 once you consider blanking; and yet we state support for that. Do these specs include blanking?