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AM572x VIP resolution support

radar
Expert 3550 points

Champs, I am confused by the AM572x VIP section of the TRM, which is to say I've read it...

So probably the simplest question I can ask is, what is the maximum number of PCLKs between falling edges of HSYNC that the VIP on AM572x can handle (and maybe pursuant to this; what register or TRM section should I have been looking at to have determined this for myself)?

Specifically at this point, just high level; the module states support for things close to 4K..

It says:

  • Supports up to 2047 pixels wide input - when scaling is engaged

  • Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without scaling

  • Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling

  • The maximum input resolution support is further limited by pixel clock and feature-dependent constraint

So... it would seem that we can get close to a 4K input; which is what I'm trying to do- specifically 4000 pixels/line.  Now that said though; it seems I am close to the limit; but these limits seem to be related ot scaling and chroma subsampling functions; which would only be applicable to the ACTIVE pixels, NOT the blanking, correct? That is, a 4000 pixel wide input; probably has close to 4300 or so actual PCLKs per line; 4000 active ones and maybe 7-10% blanked.  I would guess even a 3840 wide input is over 4096 once you consider blanking; and yet we state support for that.  Do these specs include blanking?


  • 0
    TI__Guru**** 393215 points
    Hi,

    As stated in the TRM "The maximum input resolution support is further limited by pixel clock and feature-dependent constraint". You must determine your required frame size and frames per second. From these you can calculate roughly the required pixel clock. You will be able to see if this required clock rate is supported by the device.
  • 0 in reply to Biser Gatchev-XID
    TI__Expert 3550 points
    Okay, this did not answer the question. The pixel clock rate is NOT the limiting factor; I could reduce frame rate to impact that. The question was:

    "what is the maximum number of PCLKs between falling edges of HSYNC that the VIP on AM572x can handle (and maybe pursuant to this; what register or TRM section should I have been looking at to have determined this for myself)?" I never asked about frequency.

    My concern here is NOT the PCLK rate; the concern is that the part has some hard limit, like maybe 12 bit counters or something, that says no matter how slow I run PCLK, I won't be able to accommodate an input at greater than X pixels. The problem is, I can't find what register I should be looking at that would define that upper bound.
  • 0 in reply to radar
    TI__Mastermind 22946 points

    Hi,

    You are referring to the right section in TRM. The width referred there is the active pixels that needs processing. However, note that 4K pixels is for 16 bit input data (YUV interleaved) but if you are bringing in RGB24 bit, then the resolution reduces to 2730 pixels (see below line in bold). Next revision of TRM will have this clarifications. This because the internal VPDMA line buffer width is limited to 8K bytes. Also wanted to make it clear that if any other processing block inside VIP like scaling or chroma sampling is turned ON, then the you can not bring 4K data in as the line buffer width of those processing block is smaller and will guide the max resolution that can be brought in.

    • Supports up to 2047 pixels wide input - when scaling is engaged

    • Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without scaling

    • Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling

    • The maximum supported input resolution is further limited:

      • By pixel clock and feature-dependent constraints

      • For RGB24-bit format (RAW data), the maximum frame width is limited to 2730 pixels

  • 0 in reply to Manisha Agrawal
    TI__Expert 3550 points

    So I think I finally got to the answer to the question I asked by goign to an internal design spec; but for the benfit of those who don't have access to it; the 'real' answer reduces to:


    1) per your commentary; the active line buffer must be 8K bytes or less

    2) the total line length; that is; with sync/blank, is actually immaterial, it's only teh active pixels that both the 8K limit on bytes, and the other quoted pixel limits refer to.

    So those are the limits; my only comment (and I made this to RJ internally as well); is that for cleanup of the TRM, if the numbers quoted (the 3840/4000/4095 and 2730) added the word 'active pixels' or something similar; that would have cleared it up.  I had also suggested some verbage to the point that the overhead of sync/blanking really doesn't matter for this VIP input; it's only the active pixels that start getting you into these restrictions.