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AM335X pvrsrvctl failing, non-linefetch

Other Parts Discussed in Thread: DA8XX, AM3358, AM3356, AM3352, AM3359, AM3354

Hello,

I have a known, working kernel image and filesystem that I am porting to a new hardware platform. The only changes should be DTB image used during boot. Now the Qt5 run environment is not initializing properly. If I load all the missing kernel modules and then run "pvrsrvctl --start --no-module" it fails as follows.

[  409.626186] Unhandled fault: external abort on non-linefetch (0x1008) at 0xd2000ca8
[  409.634417] Internal error: : 1008 [#1] SMP ARM
[  409.639266] Modules linked in: bufferclass_ti(O) omaplfb(O) pvrsrvkm(O) snd_soc_omap snd_pcm_dmaengine snd_soc_core snd_compress regmap_spi snd_pcm snd_page_alloc snd_timer snd soun6
[  409.662928] CPU: 0 PID: 1780 Comm: pvrsrvctl Tainted: G           O 3.12.30-AM335x-PD15.1.1 #1
[  409.672132] task: cd0e4c00 ti: cc03e000 task.ti: cc03e000
[  409.678134] PC is at PollForValueKM+0x5c/0xc8 [pvrsrvkm]
[  409.683907] LR is at PollForValueKM+0x44/0xc8 [pvrsrvkm]
[  409.689595] pc : [<bf1042ec>]    lr : [<bf1042d4>]    psr: 80080013
[  409.689595] sp : cc03fc08  ip : cc03fc08  fp : cc03fc3c
[  409.701853] r10: 000f4240  r9 : 00000000  r8 : d2000ca8
[  409.707435] r7 : 00000000  r6 : 00000000  r5 : 00000001  r4 : 06888410
[  409.714408] r3 : f9777bf0  r2 : 06888411  r1 : 000003e8  r0 : 00000001
[  409.721387] Flags: Nzcv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment user
[  409.729008] Control: 10c5387d  Table: 8c454019  DAC: 00000015
[  409.735151] Process pvrsrvctl (pid: 1780, stack limit = 0xcc03e248)
[  409.741848] Stack: (0xcc03fc08 to 0xcc040000)
[  409.746518] fc00:                   06888411 000000ff cc03fc2c cc35c000 00000001 d145e120
...
[  410.026391] Backtrace: 
[  410.029284] [<bf104290>] (PollForValueKM+0x0/0xc8 [pvrsrvkm]) from [<bf113438>] (SGXResetInvalDC.isra.4+0x64/0x70 [pvrsrvkm])
[  410.041624] [<bf1133d4>] (SGXResetInvalDC.isra.4+0x0/0x70 [pvrsrvkm]) from [<bf1134f4>] (SGXReset+0x8c/0x1c0 [pvrsrvkm])
[  410.053230]  r4:cc35c000
[  410.056216] [<bf113468>] (SGXReset+0x0/0x1c0 [pvrsrvkm]) from [<bf10ffc0>] (SGXInitialise+0x6c/0x18c [pvrsrvkm])
[  410.067077]  r6:d145e120 r5:00000000 r4:cc35c000 r3:00000001
[  410.073444] [<bf10ff54>] (SGXInitialise+0x0/0x18c [pvrsrvkm]) from [<bf1138f0>] (SGXPostPowerState.part.4+0x44/0x98 [pvrsrvkm])
[  410.085696]  r9:00000003 r8:d1036000 r7:00000006 r6:cb83ad80 r5:cc35c000
r4:00000000
[  410.094412] [<bf1138ac>] (SGXPostPowerState.part.4+0x0/0x98 [pvrsrvkm]) from [<bf11399c>] (SGXPostPowerState+0x28/0x34 [pvrsrvkm])
[  410.106942]  r6:00000000 r5:00000000 r4:cc4b6500
[  410.112123] [<bf113974>] (SGXPostPowerState+0x0/0x34 [pvrsrvkm]) from [<bf0feaf8>] (PVRSRVDevicePostPowerStateKM_AnyVaCb+0x78/0x94 [pvrsrvkm])
[  410.125933] [<bf0fea80>] (PVRSRVDevicePostPowerStateKM_AnyVaCb+0x0/0x94 [pvrsrvkm]) from [<bf1071f8>] (List_PVRSRV_POWER_DEV_PVRSRV_ERROR_Any_va+0x50/0x60 [pvrsrvkm])
[  410.141793]  r5:bf0fea80 r4:cc03fd50
[  410.145808] [<bf1071a8>] (List_PVRSRV_POWER_DEV_PVRSRV_ERROR_Any_va+0x0/0x60 [pvrsrvkm]) from [<bf0fecf8>] (PVRSRVSetDevicePowerStateKM+0x58/0x74 [pvrsrvkm])
[  410.160837]  r3:00000000 r2:00000000 r1:bf0fea80
[  410.165808]  r6:bf11e6bc r5:00000000 r4:00000000
[  410.170982] [<bf0feca0>] (PVRSRVSetDevicePowerStateKM+0x0/0x74 [pvrsrvkm]) from [<bf110de4>] (SGXScheduleCCBCommandKM+0x6c/0xc8 [pvrsrvkm])
[  410.184341]  r6:cc03fdc0 r5:ffffffff r4:cb83ad80
[  410.189577] [<bf110d78>] (SGXScheduleCCBCommandKM+0x0/0xc8 [pvrsrvkm]) from [<bf10f6ac>] (SGXGetMiscInfoUkernel.isra.5+0x80/0xf4 [pvrsrvkm])
[  410.203032]  r7:00000000 r6:d145e180 r5:cb83ad80 r4:cc48d7c0
[  410.209392] [<bf10f62c>] (SGXGetMiscInfoUkernel.isra.5+0x0/0xf4 [pvrsrvkm]) from [<bf10f7ac>] (SGXDevInitCompatCheck+0x8c/0x2a8 [pvrsrvkm])
[  410.222755]  r9:00000003 r8:d1036000 r7:cc48d7c0 r6:d1036000 r5:00000000
r4:cc35c000
[  410.231407] [<bf10f720>] (SGXDevInitCompatCheck+0x0/0x2a8 [pvrsrvkm]) from [<bf104114>] (PVRSRVDevInitCompatCheck+0x1c/0x28 [pvrsrvkm])
[  410.244400]  r7:d1035000 r6:d1036000 r5:00000000 r4:bf104120
[  410.250675] [<bf1040f8>] (PVRSRVDevInitCompatCheck+0x0/0x28 [pvrsrvkm]) from [<bf104130>] (PVRSRVFinaliseSystem_CompatCheck_AnyCb+0x10/0x14 [pvrsrvkm])
[  410.265337] [<bf104120>] (PVRSRVFinaliseSystem_CompatCheck_AnyCb+0x0/0x14 [pvrsrvkm]) from [<bf106fa8>] (List_PVRSRV_DEVICE_NODE_PVRSRV_ERROR_Any+0x3c/0x48 [pvrsrvkm])
[  410.281475] [<bf106f6c>] (List_PVRSRV_DEVICE_NODE_PVRSRV_ERROR_Any+0x0/0x48 [pvrsrvkm]) from [<bf1040e8>] (PVRSRVFinaliseSystem+0x48/0x58 [pvrsrvkm])
[  410.295761]  r5:d1035000 r4:bf11e750
[  410.299839] [<bf1040a0>] (PVRSRVFinaliseSystem+0x0/0x58 [pvrsrvkm]) from [<bf115658>] (PVRSRVInitSrvDisconnectBW+0x50/0x7c [pvrsrvkm])
[  410.312672]  r4:00000000 r3:bf11c5fc
[  410.316785] [<bf115608>] (PVRSRVInitSrvDisconnectBW+0x0/0x7c [pvrsrvkm]) from [<bf116c44>] (BridgedDispatchKM+0xfc/0x154 [pvrsrvkm])
[  410.329433]  r6:00000045 r5:cc511300 r4:cc03fecc r3:cc511300
[  410.335773] [<bf116b48>] (BridgedDispatchKM+0x0/0x154 [pvrsrvkm]) from [<bf10eb40>] (PVRSRV_BridgeDispatchKM+0xf8/0x208 [pvrsrvkm])
[  410.348329]  r8:cb830840 r7:00000000 r6:c01c6745 r5:cb830840 r4:000006f4
r3:00000000
[  410.356885] [<bf10ea48>] (PVRSRV_BridgeDispatchKM+0x0/0x208 [pvrsrvkm]) from [<c0110678>] (do_vfs_ioctl+0x418/0x600)
[  410.368061]  r6:cb830840 r5:be8529dc r4:cb887508
[  410.373031] [<c0110260>] (do_vfs_ioctl+0x0/0x600) from [<c01108d8>] (SyS_ioctl+0x78/0x88)
[  410.381718]  r9:00000003 r8:cb830840 r7:00000000 r6:c01c6745 r5:be8529dc
r4:00000000
[  410.390157] [<c0110860>] (SyS_ioctl+0x0/0x88) from [<c0014660>] (ret_fast_syscall+0x0/0x30)
[  410.399029]  r9:cc03e000 r8:c0014808 r7:00000036 r6:00000001 r5:00000014
r4:00012008
[  410.407444] Code: e0643006 e0830002 e150000a 2a000012 (e5983000) 
[  410.413938] ---[ end trace 746407ce8e7d0b80 ]---


Also, I get these errors in the boot messages

[    0.244635] platform mpu.2: FIXME: clock-name 'fck' DOES NOT exist in dt!                                                                                                             
[    0.247945] platform 49000000.edma: FIXME: clock-name 'fck' DOES NOT exist in dt!                                                                                                     
[    0.252061] OMAP GPIO hardware version 0.1                                                                                                                                            
[    0.280279] omap-gpmc 50000000.gpmc: could not find pctldev for node /pinmux@44e10800/pinmux_nandflash, deferring probe                                                               
[    0.280364] platform 50000000.gpmc: Driver omap-gpmc requests probe deferral                                                                                                          
[    0.281566] platform 56000000.sgx: FIXME: clock-name 'fck' DOES NOT exist in dt!    

My best guess is the sgx fck error. However I do not know what would cause this problem.

Ideas?

  • Hi,

    Which Linux version is this? Please post the log before the abort.
  • Hello Biser,

    The log is the result of the following command " /usr/bin/pvrsrvctl --start --no-module"

    Here is the output from the gfx_status.sh script. All the version information you need should be here.

    root@phycore-am335x-1:~# cat gfx_status.txt

    WSEGL settings
    [default]
    WindowSystem=libpvrPVR2D_FRONTWSEGL.so.1
    ------
    ARM CPU information
    processor : 0
    model name : ARMv7 Processor rev 2 (v7l)
    Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpd32
    CPU implementer : 0x41
    CPU architecture: 7
    CPU variant : 0x3
    CPU part : 0xc08
    CPU revision : 2

    Hardware : Generic AM33XX (Flattened Device Tree)
    Revision : 0000
    Serial : 0000000000000000
    ------
    SGX driver information
    Version SGX_DDK_Linux_CustomerTI sgxddk 1.10@2359475 (release) /home/mueller-klieser/builds/AM335x-PD15.1.1/releasebuild/build/tmp-glibc/work/phycore_am335x_1-phytec-linux-gnueabi/omapM
    System Version String: None
    ------
    Framebuffer settings

    mode "800x480"
    geometry 800 480 800 480 32
    timings 0 0 0 0 0 0 0
    accel true
    rgba 8/16,8/8,8/0,8/24
    endmode

    Frame buffer device information:
    Name :
    Address : 0x8e100000
    Size : 1536000
    Type : PACKED PIXELS
    Visual : TRUECOLOR
    XPanStep : 1
    YPanStep : 1
    YWrapStep : 0
    LineLength : 3200
    Accelerator : No
    ------
    Rotation settings
    0
    ------
    Kernel Module information
    Module Size Used by
    bufferclass_ti 5429 0
    omaplfb 11565 0
    pvrsrvkm 175241 2 bufferclass_ti,omaplfb
    snd_soc_omap 2510 0
    snd_pcm_dmaengine 3025 1 snd_soc_omap
    snd_soc_core 99747 1 snd_soc_omap
    snd_compress 7598 1 snd_soc_core
    regmap_spi 1477 1 snd_soc_core
    snd_pcm 71724 3 snd_soc_core,snd_soc_omap,snd_pcm_dmaengine
    snd_page_alloc 4851 1 snd_pcm
    snd_timer 17146 1 snd_pcm
    snd 47071 4 snd_soc_core,snd_timer,snd_pcm,snd_compress
    soundcore 5060 1 snd
    da8xx_fb 12634 1 omaplfb
    cfbfillrect 3401 1 da8xx_fb
    cfbimgblt 2193 1 da8xx_fb
    cfbcopyarea 4908 1 da8xx_fb
    cryptodev 31494 0
    ipv6 268927 14
    ------
    Boot settings
    console=ttyO0,115200n8 root=ubi0:rootfs rw rootfstype=ubifs ubi.mtd=rootfs consoleblank=0
    ------
    Linux Kernel version
    Linux phycore-am335x-1 3.12.30-AM335x-PD15.1.1 #1 SMP Mon Feb 15 16:30:10 PST 2016 armv7l GNU/Linux

    THANKS

  • Hi,

    The Unhalted fault error, points to the following two most probable setting errors:
    1. You haven't enabled the clocks to the module, whose address space you're trying to access.
    or
    2. You haven't mapped the address space, you're trying to access, to the kernel virtual address space.

    Looking at your log, I'd say this is a clock issue. Could you please share your DTS & highlight the changes you've made, because I am not famliar & don't have the phycore-am335x-1 3.12.30-AM335x-PD15.1.1 mainline kernel sources ? Also which AM335x processor are you using (am3352, am3356, am3358 or AM3359)?

    Best Regards,
    Yordan
  • Hello Yordan,

    Thank you for your response. First, here is the boot log prior to the "FIXME" clock messages. I don't believe there is anything here of interested but this information was requested.

    [    0.000000] Memory: 216260K/259072K available (6171K kernel code, 577K rwdata, 2032K rodata, 396K init, 250K bss, 42812K reserved, 0K highmem)                                        
    [    0.000000] Virtual kernel memory layout:                                                                                                                                             
    [    0.000000]     vector  : 0xffff0000 - 0xffff1000   (   4 kB)                                                                                                                         
    [    0.000000]     fixmap  : 0xfff00000 - 0xfffe0000   ( 896 kB)                                                                                                                         
    [    0.000000]     vmalloc : 0xd0800000 - 0xff000000   ( 744 MB)                                                                                                                         
    [    0.000000]     lowmem  : 0xc0000000 - 0xd0000000   ( 256 MB)                                                                                                                         
    [    0.000000]     pkmap   : 0xbfe00000 - 0xc0000000   (   2 MB)                                                                                                                         
    [    0.000000]     modules : 0xbf000000 - 0xbfe00000   (  14 MB)                                                                                                                         
    [    0.000000]       .text : 0xc0008000 - 0xc080b08c   (8205 kB)                                                                                                                         
    [    0.000000]       .init : 0xc080c000 - 0xc086f340   ( 397 kB)                                                                                                                         
    [    0.000000]       .data : 0xc0870000 - 0xc0900788   ( 578 kB)                                                                                                                         
    [    0.000000]        .bss : 0xc0900790 - 0xc093f19c   ( 251 kB)                                                                                                                         
    [    0.000000] Hierarchical RCU implementation.                                                                                                                                          
    [    0.000000]  RCU restricting CPUs from NR_CPUS=2 to nr_cpu_ids=1.                                                                                                                     
    [    0.000000] NR_IRQS:16 nr_irqs:16 16                                                                                                                                                  
    [    0.000000] IRQ: Found an INTC at 0xfa200000 (revision 5.0) with 128 interrupts                                                                                                       
    [    0.000000] Total of 128 interrupts on 1 active controller                                                                                                                            
    [    0.000000] OMAP clockevent source: timer2 at 25000000 Hz                                                                                                                             
    [    0.000000] sched_clock: 32 bits at 25MHz, resolution 40ns, wraps every 171798ms                                                                                                      
    [    0.000000] OMAP clocksource: timer1 at 25000000 Hz                                                                                                                                   
    [    0.000000] Console: colour dummy device 80x30                                                                                                                                        
    [    0.000740] Calibrating delay loop... 199.06 BogoMIPS (lpj=995328)                                                                                                                    
    [    0.069341] pid_max: default: 32768 minimum: 301                                                                                                                                      
    [    0.069639] Security Framework initialized                                                                                                                                            
    [    0.069791] Mount-cache hash table entries: 512                                                                                                                                       
    [    0.095245] CPU: Testing write buffer coherency: ok                                                                                                                                   
    [    0.096124] CPU0: thread -1, cpu 0, socket -1, mpidr 0                                                                                                                                
    [    0.096256] Setting up static identity map for 0xc060c1f0 - 0xc060c260                                                                                                                
    [    0.098205] Brought up 1 CPUs                                                                                                                                                         
    [    0.098241] SMP: Total of 1 processors activated.                                                                                                                                     
    [    0.098264] CPU: All CPU(s) started in SVC mode.                                                                                                                                      
    [    0.100073] devtmpfs: initialized                                                                                                                                                     
    [    0.111138] VFP support v0.3: implementor 41 architecture 3 part 30 variant c rev 3                                                                                                   
    [    0.193845] omap_hwmod: debugss: _wait_target_disable failed                                                                                                                          
    [    0.197493] omap_hwmod: rtc: cannot be enabled for reset (3)                                                                                                                          
    [    0.199047] pinctrl core: initialized pinctrl subsystem                                                                                                                               
    [    0.201559] regulator-dummy: no parameters                                                                                                                                            
    [    0.206756] NET: Registered protocol family 16                                                                                                                                        
    [    0.213398] DMA: preallocated 256 KiB pool for atomic coherent allocations                                                                                                            
    [    0.221853] cpuidle: using governor ladder                                                                                                                                            
    [    0.221896] cpuidle: using governor menu
    [    0.244635] platform mpu.2: FIXME: clock-name 'fck' DOES NOT exist in dt!

    Attached you will find the current DTS file. We started with an evaluation board from PHYTEC for our development. Then we migrated to a custom board. In the process DTS file with no dependencies on the original PHYTEC files.

    Regarding the processor, it is TI AM3354 @300MHz. Another thing that I just noticed is that this processor version does not have GPU support. Could this be the issue?

    Thanks

    /*
     * Copyright (C) 2015 AC Squared Enterprises, Inc.
     * Author: Allen Curtis <ajcurtis@ac2enterprises.com>
     */
    
    
    /dts-v1/;
    
    /*#include "am335x-phycore-som.dtsi"*/
    #include "am33xx.dtsi"
    
    / {
    	model = "Avenu Ellipsys X5";
    	compatible = "avenu,ellipsys", "phytec,am335x-phycore-som", "ti,am33xx";
    
    	aliases {
    		rtc2 = &i2c_em3027; /* also part of the kernel configuration */
    	};
    
    	cpus {
    		cpu@0 {
    			cpu0-supply = <&vcc3v3>;
    		};
    	};
    
    	memory {
    		device_type = "memory";
    		reg = <0x80000000 0x20000000>; /* 512 MB */
    	};
    
    	backlight: lcd_backlight {
    		compatible = "gpio-leds";
    	};
    
    	user_leds: leds {
    		compatible = "gpio-leds";
    	};
    
    	panel: panel {
    		compatible = "ti,tilcdc,panel";
    		pinctrl-names = "default";
    		pinctrl-0 = <&lcd_pins>;
    		status = "okay";
    
    		panel-info {
    			ac-bias = <255>;
    			ac-bias-intrpt = <0>;
    			dma-burst-sz = <16>;
    			bpp = <32>;
    			fdd = <0x80>;
    			sync-edge = <0>;
    			sync-ctrl = <1>;
    			raster-order = <0>;
    			fifo-th = <0>;
    			invert-pxl-clk = <1>;
    		};
    
    		display-timings {
    			native-mode = <&timing0>;
    			timing0: ETM0700G0DH6 {
    				clock-frequency	= <30000000>;
    				hactive = <800>;
    				vactive = <480>;
    				hfront-porch = <40>;
    				hback-porch = <88>;
    				hsync-len = <48>;
    				vback-porch = <32>;
    				vfront-porch = <13>;
    				vsync-len = <3>;
    				hsync-active = <0>;
    				vsync-active = <0>;
    			};
    		};
    	};
            vbat: fixedregulator@0 {
                    compatible = "regulator-fixed";
                    regulator-name = "vbat";
                    regulator-min-microvolt = <5000000>;
                    regulator-max-microvolt = <5000000>;
                    regulator-boot-on;
            };
    	vcc3v3: fixedregulator@1 {
    		compatible = "regulator-fixed";
    		regulator-name = "vcc3v3";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		regulator-always-on;
    		regulator-boot-on;
    	};
    	lcd_3v3: fixedregulator-lcd {
    		compatible = "regulator-fixed";
    		regulator-name = "lcd_3v3";
    		regulator-min-microvolt = <3300000>;
    		regulator-max-microvolt = <3300000>;
    		regulator-boot-on;
    	};
    };
    
    /* I2C Busses */
    &am33xx_pinmux {
    	i2c0_pins: pinmux_i2c0 {
    		pinctrl-single,pins = <
    			0x188 (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
    			0x18c (PIN_INPUT_PULLUP | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
    		>;
    	};
    };
    
    &i2c0 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&i2c0_pins>;
    	clock-frequency = <400000>;
    	status = "okay";
    
    	tps: pmic@2d {
    		reg = <0x2d>;
    	};
    
    	i2c_eeprom: eeprom@52 {
    		compatible = "at,24c32";
    		pagesize = <32>;
    		reg = <0x52>;
    		status = "disabled";
    	};
    
    	i2c_rtc: rtc@68 {
    		compatible = "mc,rv4162c7";
    		reg = <0x68>;
    		status = "disabled";
    	};
    };
    
    /* Ellipsys RTC */
    &i2c0 {
    	i2c_em3027: rtc2@56 {
    		compatible = "em,em3027";
    		reg = <0x56>;
    		status = "ok";
    	};
    };
    
    /* SPI Busses */
    &am33xx_pinmux {
    	spi0_pins: pinmux_spi0 {
    		pinctrl-single,pins = <
    			0x150 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_clk.spi0_clk */
    			0x154 (PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d0.spi0_d0 */
    			0x158 (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d1.spi0_d1 */
    			0x15c (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_cs0.spi0_cs0 */
    			0x160 (PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_cs1.spi0_cs1 */
    		>;
    	};
    };
    
    &spi0 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&spi0_pins>;
    	status = "okay";
    
    	serial_flash: m25p80@0 {
    		compatible = "m25p80";
    		spi-max-frequency = <48000000>;
    		reg = <0x0>;
    		#address-cells = <1>;
    		#size-cells = <1>;
    		m25p,fast-read;
    	};
    
    	ellipsys_spi: stm32f100@1 {
            compatible = "spidev";
    /*        compatible = "avenu,ellipsys";*/
    		spi-max-frequency = <1000000>;
    		reg = <0x1>;
    		#address-cells = <1>;
    		#size-cells = <1>;
    	};		
    };
    /* UARTs */
    &am33xx_pinmux {
    	uart0_pins: pinmux_uart0 {
    		pinctrl-single,pins = <
    			0x170 (PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */
    			0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
    		>;
    	};
    
    	uart1_pins: pinmux_uart1 {
    		pinctrl-single,pins = <
    			0x180 (PIN_INPUT_PULLUP | MUX_MODE0)	/* uart1_rxd.uart1_rxd */
    			0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_txd.uart1_txd */
    			0x178 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* uart1_ctsn.uart1_ctsn */
    			0x17c (PIN_INPUT | MUX_MODE0)		/* uart1_rtsn.uart1_rtsn */
    		>;
    	};
    };
    &uart0 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart0_pins>;
    	status = "okay";
    };
    &uart1 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&uart1_pins>;
    	status = "okay";
    };
    
    &serial_flash {
    	label = "user";
    /*	status = "disabled";*/
    };
    
    /* NAND */
    &am33xx_pinmux {
    		nandflash_pins: pinmux_nandflash {
    			pinctrl-single,pins = <
    			0x0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
    			0x4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
    			0x8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
    			0xc (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
    			0x10 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
    			0x14 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
    			0x18 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
    			0x1c (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
    			0x70 (PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
    			0x7c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
    			0x90 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
    			0x94 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
    			0x98 (PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
    			0x9c (PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
    		>;
    	};
    };
    
    &elm {
    	status = "okay";
    };
    
    &gpmc {
    	status = "okay";
    	pinctrl-names = "default";
    	pinctrl-0 = <&nandflash_pins>;
    	ranges = <0 0 0x08000000 0x10000000>;   /* CS0: NAND */
    	nandflash: nand@0,0 {
    		reg = <0 0 0>; /* CS0, offset 0 */
    		nand-bus-width = <8>;
    		ti,nand-ecc-opt = "bch8";
    		gpmc,device-nand = "true";
    		gpmc,device-width = <1>;
    		gpmc,sync-clk-ps = <0>;
    		gpmc,cs-on-ns = <0>;
    		gpmc,cs-rd-off-ns = <30>;
    		gpmc,cs-wr-off-ns = <30>;
    		gpmc,adv-on-ns = <0>;
    		gpmc,adv-rd-off-ns = <30>;
    		gpmc,adv-wr-off-ns = <30>;
    		gpmc,we-on-ns = <0>;
    		gpmc,we-off-ns = <20>;
    		gpmc,oe-on-ns = <10>;
    		gpmc,oe-off-ns = <30>;
    		gpmc,access-ns = <30>;
    		gpmc,rd-cycle-ns = <30>;
    		gpmc,wr-cycle-ns = <30>;
    		gpmc,wait-on-read = "true";
    		gpmc,wait-on-write = "true";
    		gpmc,bus-turnaround-ns = <0>;
    		gpmc,cycle2cycle-delay-ns = <50>;
    		gpmc,cycle2cycle-diffcsen;
    		gpmc,clk-activation-ns = <0>;
    		gpmc,wait-monitoring-ns = <0>;
    		gpmc,wr-access-ns = <30>;
    		gpmc,wr-data-mux-bus-ns = <0>;
    
    		elm_id = <&elm>;
    
    		#address-cells = <1>;
    		#size-cells = <1>;
    	};
    };
    &nandflash {
    	partition@0 {
    		label = "spl";
    		reg = <0x0 0x200000>;
    	};
    
    	partition@1 {
    		label = "u-boot";
    		reg = <0x200000 0x100000>;
    	};
    
    	partition@2 {
    		label = "u-boot-env";
    		reg = <0x300000 0x100000>;
    	};
    
    	partition@3 {
    		label = "dtb";
    		reg = <0x400000 0x100000>;
    	};
    
    	partition@4 {
    		label = "splash";
    		reg = <0x500000 0x400000>;
    	};
    
    	partition@5 {
    		label = "kernel";
    		reg = <0x900000 0x600000>;
    	};
    
    	partition@6 {
    		label = "rootfs";
    		/*
    		 * setting size to 0x0 here, size will be extended to
    		 * end of nand flash while booting.
    		 */
    		reg = <0xf00000 0x0>;
    	};
    };
    
    /* MCU GPIOs */
    &am33xx_pinmux {
    	pinctrl-names = "default";
    	/* pinctrl-0 = <&interlock_gpio_pins &user_buttons_pins &spi_flowctl_gpio_pins>; */
    	pinctrl-0 = <&interlock_gpio_pins &spi_flowctl_gpio_pins>;
    
    	mcu_reset_gpio_pins: pinmux_mcu_reset_gpio {
    		pinctrl-single,pins = <
    			/* only drive this when rebooting the MCU */
    			0x16C (PIN_INPUT_PULLUP | MUX_MODE7)	/* BootMode0.gpio1_9 */
    			0x194 (PIN_INPUT_PULLUP | MUX_MODE7)	/* BootMode0.gpio3_19 */
    		>;
    	};
    
    	mcu_boot0_gpio_pins: pinmux_mcu_boot0_gpio {
    		pinctrl-single,pins = <
    			/* only drive this when rebooting the MCU */
    			0x16C (PIN_INPUT_PULLUP | MUX_MODE7)	/* uart0_rtsn.gpio1_9 */
    		>;
    	};
    
    	spi_flowctl_gpio_pins: pinmux_spi_flowctl_gpio {
    		pinctrl-single,pins = <
    			0x134 (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpio2_18 */
    			0x12C (PIN_INPUT_PULLUP | MUX_MODE7)	/* gpio3_9 */
    		>;
    	};
    
    	interlock_gpio_pins: pinmux_interlock_gpio {
    		pinctrl-single,pins = <
    			0x11C (PIN_INPUT_PULLUP | MUX_MODE7)	/* From MCU,gpio0_16 */
    			0x80 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* To MCU,gpio1_30 */
    		>;
    	};
    
    /* Buttons are handled by the MCU right now
    	user_buttons_pins: pinmux_user_buttons {
    		pinctrl-single,pins = <
    			0x1E4 (PIN_INPUT_PULLUP | MUX_MODE7)	// emu0.gpio3_7 
    			0x1E8 (PIN_INPUT_PULLUP | MUX_MODE7)	// emu1.gpio3_8 
    		>;
    	};
    */
    };
    
    /* USB */
    &usb {
    	pinctrl-names = "default";
    	pinctrl-0 = <&usb_pins>;
    	status = "okay";
    };
    &am33xx_pinmux {
    	usb_pins: pinmux_usb_pins {
    		pinctrl-single,pins = <
    			0x21c (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	/* usb0_drvvbus.usb0_drvvbus */
    			/* 0x234 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)	 usb1_drvvbus.usb1_drvvbus */
    	/* NOT SURE WHAT THESE GPIOs are USED FOR */
    			/* 0x80 (PIN_INPUT_PULLUP | MUX_MODE7)	 gpmc_csn1.gpio1_30 */
    			/* 0x84 (PIN_INPUT_PULLUP | MUX_MODE7)	 gpmc_csn2.gpio1_31 */
    		>;
    	};
    };
    &cppi41dma {
    	status = "okay";
    };
    &ctrl_mod {
    	status = "okay";
    };
    &usb0 {
    	dr_mode = "host";
    	status = "okay";
    };
    &usb0_phy {
    	status = "okay";
    };
    
    /* MMC */
    &am33xx_pinmux {
    	mmc1_pins: pinmux_mmc1_pins {
    		pinctrl-single,pins = <
    			0x0f0 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat3 */
    			0x0f4 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat2 */
    			0x0f8 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat1 */
    			0x0fc (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_dat0 */
    			0x100 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_clk */
    			0x104 (PIN_INPUT_PULLUP | MUX_MODE0)	/* mmc0_cmd */
    			/* pullup already wired,  function: SD0_WP write protect */
    			0x1a0 (PIN_INPUT_PULLDOWN | MUX_MODE4)	/* mcasp0_aclkr.mmc0_sdwp_mux1 */
    			/* pullup already wired, function: nSD0_CD card detect */
    			0x044 (PIN_INPUT | MUX_MODE7)    /* gpmc_a1.gpio1[17] */
    		>;
    	};
    };
    
    &mmc1 {
    	pinctrl-names = "default";
    	pinctrl-0 = <&mmc1_pins>;
    	vmmc-supply = <&vcc3v3>;
    	bus-width = <4>;
    	cd-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
    	status = "okay";
    };
    
    /* LCD Panel */
    &am33xx_pinmux {
    	lcd_pins: pinmux_lcd {
    		pinctrl-single,pins = <
    			0xA0 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data0.lcd_data0 */
    			0xA4 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data1.lcd_data1 */
    			0xA8 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data2.lcd_data2 */
    			0xAC (PIN_OUTPUT | MUX_MODE0)	/* lcd_data3.lcd_data3 */
    			0xB0 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data4.lcd_data4 */
    			0xB4 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data5.lcd_data5 */
    			0xB8 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data6.lcd_data6 */
    			0xBC (PIN_OUTPUT | MUX_MODE0)	/* lcd_data7.lcd_data7 */
    			0xC0 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data8.lcd_data8 */
    			0xC4 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data9.lcd_data9 */
    			0xC8 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data10.lcd_data10 */
    			0xCC (PIN_OUTPUT | MUX_MODE0)	/* lcd_data11.lcd_data11 */
    			0xD0 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data12.lcd_data12 */
    			0xD4 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data13.lcd_data13 */
    			0xD8 (PIN_OUTPUT | MUX_MODE0)	/* lcd_data14.lcd_data14 */
    			0xDC (PIN_OUTPUT | MUX_MODE0)	/* lcd_data15.lcd_data15 */
    			0x3C (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad15.lcd_data16 */
    			0x38 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad14.lcd_data17 */
    			0x34 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad13.lcd_data18 */
    			0x30 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad12.lcd_data19 */
    			0x2C (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad11.lcd_data20 */
    			0x28 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad10.lcd_data21 */
    			0x24 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad9.lcd_data22 */
    			0x20 (PIN_OUTPUT | MUX_MODE1)	/* gpmc_ad8.lcd_data23 */
    			0xE0 (PIN_OUTPUT | MUX_MODE0)	/* lcd_vsync.lcd_vsync */
    			0xE4 (PIN_OUTPUT | MUX_MODE0)	/* lcd_hsync.lcd_hsync */
    			0xE8 (PIN_OUTPUT | MUX_MODE0)	/* lcd_pclk.lcd_pclk */
    			0xEC (PIN_OUTPUT | MUX_MODE0)	/* lcd_ac_bias_en.lcd_ac_bias_en */
    		>;
    	};
    };
    &lcdc {
    		status = "okay";
    };
    &epwmss2 {
    		status = "okay";
    };
    &ecap2 {
    	status = "okay";
    };
    
    /* Backlight */
    &am33xx_pinmux {
    	backlight_pins: pinmux_backlight {
    		pinctrl-single,pins = <
                    	0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)  /* gpmc_a5.gpio0_28 */
                    >;
    	};
    };
    &backlight {
    	pinctrl-0 = <&backlight_pins>;
    	led0 {
    		label = "backlight:user0";
    		gpios = <&gpio0 28 GPIO_ACTIVE_HIGH>;
    	/* default trigger should be changed to "backlight" */
    		linux,default-trigger = "none";
    		default-state = "off";
    	};
    };
    
    

  • Hi, 

    Allen Curtis said:
    Regarding the processor, it is TI AM3354 @300MHz. Another thing that I just noticed is that this processor version does not have GPU support. Could this be the issue?

    Yes, this is why I wanted to know which AM335x processor are you using. 

    Can you first try to rename /etc/init.d/pvr-init to /etc/init.d/pvr-init.old (or whatever name you choose) and try to boot again.  This is how I overcame the booting issue on my BBB (with soc changed to AM3354). 

    Best Regards, 
    Yordan

  • Thanks for the help Yordan,

    The board will boot even though pvr-init fails to start. 

    It appears that Qt requires OpenGL support to run. I have notified the customer and they are getting a processor with GPU support.

    Sorry for the wild goose chase. The customer decided to change processors. It did not occur to me that different versions would not have GPU support.

    TIA