Hello,
I see in various documents the maximum SPI clock is 48MHz. I need exactly 40MHz for a custom peripheral. From document SPRUMH73M page 1144 is a peripheral PLL structure diagram and a table on the bottom of the page. It shows DIV Value=5 which gives 192MHz. It is possible to set the DIV value to 6?
This would give 160MHz the divide by 4 would be 40MHz. I'm not sure how to do this or any problems doing this to achieve 40MHz SPI Master clock rate. I'm using a BBB Rev. C.
Thanks
