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Which pin is TRACECLK of AM335x?

shigehiro tsuda
Mastermind 9490 points

Hi ,

With the technical reference manual of AM335x, TRACE port is defined in EMU0,EMU1,EMU2,EMU3,EMU4.
What pin is TRACECLK necessary for trace of ETM?

With the following gel file of CCS, I seem to choose a pin by register setting, but the details of this register do not list it in a technical reference manual.
May you output it freely as TRACECLK wherever of the EMU pin?
I think that EMU2 uses it with the following gel file as TRACECLK, is it right?

GEL file:
AM335x_trace_dapdebugss.gel

DRM_CTL(0) = (0x80000000 | DPM_MODE_STM_DATA0); // set DP0 as STM trace data0
DRM_CTL(1) = (0x80000000 | DPM_MODE_STM_DATA1); // set DP0 as STM trace data1
DRM_CTL(2) = (0x80000000 | DPM_MODE_STM_CLK ); // set DP0 as STM trace clock
DRM_CTL(3) = (0x80000000 | DPM_MODE_STM_DATA2); // set DP0 as STM trace data2
DRM_CTL(4) = (0x80000000 | DPM_MODE_STM_DATA3); // set DP0 as STM trace data3

Best Regards,

Shigehiro Tsuda

  • 0
    TI__Guru**** 393215 points

    Yes, TRACECLK is on EMU2.

  • 0 in reply to Biser Gatchev-XID
    Mastermind 9490 points
    Hi Biser,

    Thank you for quick reply.

    Is TRACECLK fixed in EMU2?
    Or when I make the following setting, will EMU4 become TRACECLK?

    DRM_CTL(0) = (0x80000000 | DPM_MODE_STM_DATA0);
    DRM_CTL(1) = (0x80000000 | DPM_MODE_STM_DATA1);
    DRM_CTL(2) = (0x80000000 | DPM_MODE_STM_DATA2 );
    DRM_CTL(3) = (0x80000000 | DPM_MODE_STM_DATA3);
    DRM_CTL(4) = (0x80000000 | DPM_MODE_STM_CLK);

    Best Regards,
    Shigehiro Tsuda
  • 0 in reply to Biser Gatchev-XID
    Mastermind 9490 points

    Hi Biser,

    Thank you for quick reply.

    The trace of 1pin mode sets follows when I refer to the following gel file.

    In this case I think that TRACECLK sets it in EMU1, is it right?

    Is TRACECLK really fixed in EMU2?

    GEL file:
    AM335x_trace_dapdebugss.gel

    DRM_CTL(0) = (0x80000000 | DPM_MODE_STM_DATA0); // set DP0 as STM trace data0
    DRM_CTL(1) = (0x80000000 | DPM_MODE_STM_CLK ); // set DP1 as STM trace clock
    DRM_CTL(2) = (0x80000000 | 0); // clear the remaining pin to set it to tri-state
    DRM_CTL(3) = (0x80000000 | 0); // clear the remaining pin to set it to tri-state
    DRM_CTL(4) = (0x80000000 | 0); // clear the remaining pin to set it to tri-state

    Best Regards,

    Shigehiro Tsuda

  • 0 in reply to shigehiro tsuda
    TI__Guru* 86060 points

    Shigehiro, the Trace clock and data mapping is flexible depending on how many trace pins you are using.  Here is some information to help you configure this.

    You can map any EMU pin to any trace data or clock signal.

    There is one control register per EMUx signal (EMU0-4), called DPM Control Register. This register is defined below. Note: there are 25 registers (0-24), but AM335x device only uses (0-4) to correspond to the number of EMU signals used.

    DebugSS_DRM register base address: 0x4B160000

    DPM control register offset: 0x80

    • DPM Control Registers (0-24)

    Bit

    Field Name

    Description

    Reset Value

    Access (R/W)

    31

    Override

    When 1, indicate reallocation to non-debug functions is not allowed.

    0

    R

    W(Dbg only)

    30

    Dbg_only

    Indicates the DP pin is for debug function only

    0

    R

    29

    App_own

    Indicates the DP pin is application owned.

    0

    R

    28

    BitIO_En

    Bit IO Enable bit. When read, this bit shows 1.

    1

    W

    27

    DP_In

    This bit shall indicate the current value of DP_In

    *

    R

    26

    DP_Out

    In BIT IO Mode, writing to this bit shall set the DP Output. Set BitIO_En to 1 before the writing.

     

    W

    Reading this bit shall indicate the current value of DP_Out.

    1

    R

    25

    DP_Oen

    In BIT IO Mode, writing to this bit shall set the DP Output-enable. Set BitIO_En to 1 before the writing.

     

    W

    Reading this bit shall indicate the current value of DP_Oen.

    1

    R

    24:8

    Reserved

     

    0

    R

    7:0

    PM_Ctrl

    Pin manager control bits

    0

    RW

    Table 9. DPM Control Register

    The PM_Ctrl bits for each register is defined below. For System Trace support, you can map any signal (data3-0 or clock) to any EMU signal

    DPMcontrol[x]

    Debug support

    Debug source

    0000

    0000

    Tri-State

    0001

    Trigger

    0010

    System Trace

    Trace Data[0]  

    0011

    Trace Data[1]

    0100

    Trace Data[2]

    0101

    Trace Data[3]

    0110

    Trace Clock

    0111

    CS Trace

    Trace Data A

    1000

    Trace Data B

    1001

    Trace Ctrl

    1010

    Trace Clock

    1011

    DSP Trace

    Trace Data A

    1100

    Trace Data B

    1101

    Trace Clock

    1110

    HS-RTDX

     

     

     

     

     

     

     

     

     

     

     

    Regards,

    James

  • 0 in reply to JJD
    Mastermind 9490 points

    Hi James,

    Thank you for quick reply.

    I understood that the mapping of TRACECLK and DATA is set depending on the register setting of the DPM controller flexibly in all EMU pin.

    I am grateful for your response.

    Best Regards,

    Shigehiro Tsuda