TMS320C6747 EDMA3/SPI randomly gets out of sync

Jack Farden

Other Parts Discussed in Thread: TMS320C6747

We have an embedded design in which we are using a MPC5566 as our master controller and the TI TMS320C6747 DSP as our signal processor. We have the 5566 setup as the SPI master and the TMS320C6747 configured as a SPI slave. We are using the EDMA3 for receiving and transmitting of 16 words. We have used the TI EDMA3 Low-level Driver 01.11.03.01 for configuration and talking to the EDMA peripheral. Our protocol has a beginning marker and end marker. Our problem is that after several hours of run time it appears that the SPI communication gets out of sync on the TMSC320C6747 end. We have verified with SPI analyzers that the 5566 is sending the correct data. Signal integrity looks great. We have attempted to slow down teh SPI clock and this seems to have no effect. The communication is getting out of sync by multiple words. some of the data the we are transmitting can still be seen in the 16 word transfer, but instead of being in location 1 and 2, it maybe 13 and 14. In some cases we can run systems for days and not see this, other units may exhibit this in a few ours, then not do it again for a day. Most recently it appears that Rev B works or and our rev D TMS320C6747 silicon exhibits this issue. Please help!!!!

over 9 years ago

0 Sivaraj Kuppuraj over 9 years ago

TI__Mastermind 35645 points

Hi,

Thanks for your post.

I have some suggestion below:

The CSHOLD bit is used to tell the hardware whether or not it should leave the chip select pin asserted between transfers. For example, if you wanted to transfer multiple words of data and needed the chip select asserted for the duration of the entire transfer you would set CSHOLD=1, write your multiple words of data, and then write CSHOLD=0 so that it de-asserts when you're finished. So again, I'm not sure how the driver is utilizing the CSHOLD bit. However, if it's being set and cleared around the transfer then may be, you could evaluate whether SPI is out of sync with C6747.

Do you see probably more delay between consecutive writes to the SPIDAT1 register and if so, this could also be the out of sync issue of SPI with c6747? If you see more delay, you could also potentially reduce the delay if you perform a 32-bit write such that you could simultaneously wrote to both the CSHOLD bit and the TXDATA field all at once.

There are notes mentioned below which can be considered if any delay cause out of sync issue:

"The previous value of the CSHOLD bit in the SPI transmit data register (SPIDAT1) must be cleared to 0

for the C2T delay to be enabled."

"The current value of the CSHOLD bit in the SPI transmit data register (SPIDAT1) must be cleared to 0 for

T2C delay to be enabled."

Also, I think, there is a PSP SPI-EDMA example available for you to benchmark the SPI-EDMA configuration on C6747 and you could utilize the same, after you install PSP, the SPI (and EDMA) example can be located at the below folder path:

~\pspdrivers_01_20_00\packages\ti\pspiom\examples\evm6747\spi\edma

Thanks & regards,

Sivaraj K

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TMS320C6747 EDMA3/SPI randomly gets out of sync