• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 98 subscribers
  • Views 545 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

C6655 internal line length

UNA
Mastermind 7980 points

Hi,

I want to know that in order to guess the actual waveform of DDR3 signal.
How much the internal line length of DDR3 terminals of C6655 package have?

Best regards,

H.U

  • 0
    TI__Mastermind 46460 points

    HU,

    This information is not available.  It is not needed to obtain a successful DDR3 layout.  The routing rules provided in the DDR3 Design Requirements for KeyStone Devices Application Report (SPRABI1B) are sufficient to obtain a robust layout.  The IBIS model can be used to validate signal integrity.

    Tom