Other Parts Discussed in Thread: 66AK2H14
Hi,
I have some questions about "MDIO Timing Requirements" in 66AK2H14.
I refer to "Table 10-49 MDIO Timing Requirements" in datasheet(sprs866e.pdf, p325).
In here, th(MDCLKH-MDIO) is defined as 10 ns.
In the MDIO specification(IEEE802.3 Std), "MDIO clock to output delay" is defined as Min = 0 ns, Max = 300 ns.
・th(MDCLKH-MDIO) in 66AK2H14 is 10 ns,
・the MDIO clock to output delay is a minimum of 0 ns.
1.
In most PHY devices, the output delay time is a minimum of 0 ns.
Therefore, I think that it cannot meet the "MDIO Timing requirements" in 66AK2H14.
To meet the "MDIO timing requirements" in 66AK2H14,
I think that the data signal(MDIO) must be delayed more than 10ns than the clock signal(MDC).
Is this correct?
2.
Is the data sheet not mistake ?
Best Regards,
Yasunori