• State Resolved
  • Locked Locked
  • Replies 9 replies
  • Subscribers 98 subscribers
  • Views 2238 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

FID definition in C6678

Allen35065
Expert 4465 points

Hi All,

In C66x Corepac UG i can see FID region in L1P Memory Protection Fault Set Register (L1PMPFSR).

Is this FID same as AID?

And in which document can I find the relationship between AID(or FID) and masters in C6678?

Thank you.

Regards,

Allen

  • 0
    TI__Genius 12805 points
    Here is what I think

    In general, both AID and FID present the requester ID. The requester ID is the ID of the host that request access to the memory. EDMA gets the requester ID from the host that initializes the transfer.

    However, the design of Memory Protection register leaves only 6 bits and the local bit, so for permission all host with ID that is more than 5 are combined together
    The Fault ID (FID) has 7 bits so if there is a fault, the user can find which requester caused the fault

    Does it make sense to you?

    Ran
  • 0 in reply to ran35366
    TI__Expert 4465 points

    Hi Ran,

    The problem I met is L1PMPFSR was 0x640 which means FID is 3. I'm not sure which master cause this issue on C6678. Is it mean core 3?

    Regards,

    Allen

  • 0 in reply to Allen35065
    TI__Expert 4465 points
    L1PMPFSR should be 0x620.
  • 0 in reply to Allen35065
    TI__Genius 12805 points
    If I put your value 0x620 (0000 0000 0000 0000 0000 011 0 0010 0000

    At table 2-20 in the C66X CorePac User's Guide I see core 1 and core 2 access

    I wonder if the code that run runs on core 1, and 2,

    Ran
  • 0 in reply to ran35366
    TI__Expert 4465 points

    Hi Ran,

    I need to add some details here because i'm confused about this FID.

    Customer's L1D MPFSR was 0x620 and this issue was on core 2 on C6678. If it was caused by core 2 itself, i think LOCAL bit should be set in this register. 

    From the FID definition, i doubt FID should be ID index of requestor. Could you please help to check this?

    FID Bit 6:0 of faulting requestor. If ID is narrower than 7 bits, the remaining bits return 0.
    If ID is wider than 7 bits, the additional bits get truncated. FID =0 if LOCAL =1.

    Thank you.

    Regards,

    Allen

  • 0 in reply to Allen35065
    TI__Genius 12805 points

    I will consult with the architects and get back when I have answer

    Ran

  • 0 in reply to ran35366
    TI__Expert 4465 points
    Hi Ran,

    Do you have any information?
    I did some tests on EVM and when i tried to use different core to write core 0's L1P address then FID of L1PMPFSR changed to the core index. So i guess FID may not be same as AID bit.

    Regards,
    Allen
  • 0 in reply to Allen35065
    TI__Genius 12805 points

    Here is what I got

    The C66x corepac userguide answers your questions below:

      http://www.ti.com/general/docs/lit/getliterature.tsp?baseLiteratureNumber=sprugw0&fileType=pdf

     

    L1PMPFSR – Section 2.8.2.3

    * FID is a fault ID, not the privid of the requester.

     

    Then I asked:

     

    So if the L1PMPFSR  register value is 0x620,  what does it mean? 

    Which requester cause the fault?  Is it a core? A peripheral?  Is it for read? For write?

    And I got the following answer:

    L1PMPFSR.LOCAL (bit 8) == 0 – indicates that the error is not locally generated

    L1PMPFSR.FID == 0x3 – indicates that this is a memory protection fault from either IDMA or SDMA, and that the PRIVID of the requestor is 0x3

    Going through the e2e conversation, I am not sure if its L1DMPFSR or L1PMPFSR – both seems to be referred to here

    If L1DMPFSR or L1PMPFSR == 0x0620 : the error is bit 5 – Supervisor Read  

    This would be a DMA (SDMA or IDMA) read from a peripheral that was on CPRICIV = 0x3, and tried a supervisor read to L1DSRAM or L1PRAM (depending on which MPFSR is being captured)

     Ran

  • 0 in reply to ran35366
    TI__Expert 4465 points

    Hi Ran,

    I see. Either SDMA or IDMA can trigger this error. It's quite helpful. Thank you very much.

    Regards,

    Allen