EDMA transfer effect HWI?

Hi,

Thanks for your post.

Did your previous transfer was completed with chain-trigger configuration? If so, any chain completion code is detected and do you see the value in the TCC corresponding to bit TCC\[5:0\] in OPT register of the PaRAM set associated with that channel?

Did you check the corresponding bit enabled in chained event register (CER)?

I mean, did the chain trigger event occurs after every transfer request is submitted to EDMACC which would queue the event in the appropriate event queue?

In general, chaining would be achieved at:

1. Either final transfer completion (ITCCHEN = 0, TCCHEN =1)

2. Or intermediate transfer completion (ITCCHEN = 1, TCCHEN =0)

3. Or both (ITCCHEN = 1, TCCHEN =1

Kindly check the below wiki resources to see for EDMA sample test application which would help you better:

http://processors.wiki.ti.com/index.php/EDMA3

http://processors.wiki.ti.com/index.php/EDMA_sample_test_application

http://processors.wiki.ti.com/index.php/Programming_the_EDMA3_using_the_Low-Level_Driver_%28LLD%29

Thanks & regards,

Sivaraj K

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