AM57x GPMC read access time

Shareef

Expert 1985 points

Other Parts Discussed in Thread: AM5728

Hi all,

We plan to interface an asynchronous memory to GPMC of AM5728. We understand that the GPMC_FCLK is same as L3_CLK which is 266MHz.

From the GPMC timing parameters, I find that maximum RDACCESSTIME / WTACCESSTIME of GPMC is 116ns (3.7593ns*31clk).
But the memory device choosen has 150ns of read/write accesstime.

1. Is there a way the GPMC can be interfaced with this memory device of higher readacess time with the same GPMC_FCLK of 266MHz? I hope this is possible using Ready/Busy signal of memory device being connected to GPMC_WAIT signal, can you please confirm this?

2. If Ready/Busy signal is not available from the memory device, then interfacing is not possible at GPMC_FCLK of 266MHz. Then lowering GPMC_FCLK or L3 Clock (such that the readaccess time of memory device is met) is the only option. Is this correct?

Thanks.

Regards,

Shareef

over 9 years ago

0 Biser Gatchev-XID over 9 years ago

TI__Guru**** 393215 points

Hi,

GPMC_FCLK is set by ROM code to 133MHz. Are you asking about a boot device or just need it for general access?

0 Shareef over 9 years ago in reply to Biser Gatchev-XID

Expert 1985 points

Hi Biser,

The memory is for general access after the board has booted up.

Regards,
Khader Shareef

0 Biser Gatchev-XID over 9 years ago in reply to Shareef

TI__Guru**** 393215 points

Well, then you can freely program all GPMC timing parameters to match your device. Refer to section 15.4 in the AM572X TRM Rev. E for full description of the GPMC interface.

0 Shareef over 9 years ago in reply to Biser Gatchev-XID

Expert 1985 points

Hi Biser,

Thanks.
Can you please confirm my statements below?

For query #1, Yes - By using Ready/Busy signal (WAIT) it is possible to interface a memory with higher read/write access time in asynchronous mode.
For query #2, Lowering L3 Clock is the only option if there is no R/B signal from memory device.

Regards,
Khader Shareef

0 Biser Gatchev-XID over 9 years ago in reply to Shareef

TI__Guru**** 393215 points

1. Yes, this is possible.
2. No, this is not necessary. All GPMC timing parameters are set in number of GPMC_FCLK cycles. You simply need to calculate the number of cycles you need to achieve the necessary time.

0 Shareef over 9 years ago in reply to Biser Gatchev-XID

Expert 1985 points

Hi Biser,

Many thanks for clarifying on query #1.

On query #2, like I had explained in my first post that the maximum RDACCESSTIME / WTACCESSTIME of AM57x GPMC is 116ns (3.7593ns*31clk) of GPMC controller considering 266MHz of GPMC_FCLK. Whereas the memory device has read/write access time of 150ns plus it does not have R/B signal to delay the timings at GPMC controller side. Only in this case do I need to lower the GPMC_FCLK to meet the read/write access time of memory?

Regards,
Khader Shareef

0 Biser Gatchev-XID over 9 years ago in reply to Shareef

TI__Guru**** 393215 points

GPMC_FCLK is set by ROM code to 133MHz.

0 Biser Gatchev-XID over 9 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

You can also use TIMEPARAGRANULARITY to double the timings.

0 Shareef over 9 years ago in reply to Biser Gatchev-XID

Expert 1985 points

Hi Biser,

Thanks, this was helpful. With the TIMEPARAGRANULARITY bit set to 0x1 (double latency) the GPMC_FCLK can remain same in this case.

Regards,
Khader Shareef

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AM57x GPMC read access time