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I am Using RTOS on DM8148 , I am trying to display an image from A8 to M3 .

Other Parts Discussed in Thread: SYSBIOS

I am Using RTOS on DM8148 , I am trying to display an image from A8 to M3. A8 is placing the data in memory while M3 is reading from that Location and displaying it . The problem is the image doesnt show up completely there are empty line in between . When i am running my function  two or three times i can see the complete image. I am using AVSDK package for DM8148

While running it without RTOS i am getting a very slow processing speed, but i am getting a whole frame in running the function single time.Please help me with this.

BR

AMMAR 

  • AMMAR,

    I'm completely unfamiliar with the AVSDK package, however, it sounds like there may be some kind of cache refresh missing on the m3 side. Does the M3 code invoke Cache_inv() on the dispay buffer before processing it? If not, then the M3 is potentially reading from cache rather than from the newly refreshed image buffer.
  • Thank you for your reply Alan,

    But thing is that when i am actually sending data from A8 to memory M3 is able to show it completely , but when i invoke RTOS on A8 as well , The data showed by M3 is not complete , its partial , like it shows half of the data , when i repeat the same data from A8 , more of the data is shown by M3 , repeating it like 4 to 5 times give me 1 frame  on M3 side . its like A8 is not releasing the memory after writing on it .

    Could you suggest how can i solve this ?

    BR

    Ammar Zafar 

  • This really sounds like a cache flush issue on the A8 side. After writing the image to the shared buffer, the A8 code must perform a Cache_wb(imageBuffer, imageBufferSize, Cache_Type_ALLD, TRUE) to push the data out of the cache.

    I suspect the reason that everything works (but very slowly) without RTOS is that the data cache is not enabled so all data writes are directly to external memory.

    Alan
  • Thank you Alan ,

    In My config file i actually havent include cache for A8 , so why i need to flush it? And why writing to it like 3 or 4 time shows me a full image ? on the other hand writing to ddr should take same time for A8 either with or without rtos because my buffer is basically on DDR3 location, Is there any kind of initialization needed that i need to add in my code while running it without an OS ?

     

  • The ti.sysbios.family.arm.a8.Cache module is automatically pulled in AND THE DATA CACHE IS ENABLED for the entire DDR address space when an A8 RTOS application is built. That is why the RTOS application runs faster than the non-RTOS application.

    Because the cache is enabled, the A8 application must flush the contents of the cache that maps to the image buffer in order to force the data out to the DDR so that the M3 can read it.

    Without an explicit cache flush operation, the cached image buffer may or may not ever find its way out to the DDR. The ARM A8's L1/L2 cache behavior is not well-specified. Only when more room in the L1/L2 cache is required for new memory address read or writes will the stale contents be flushed to external memory. Precisely when this happens depends on the application's memory access behavior.

    Alan
  • Thank You Alan , this worked !!
    One more thing does C674 dsp core do the same as A8 does ?

    BR
    Ammar Zafar
  • The internal design of the Cache module for the C674 dsp core is necessarily different than the Cache module for the A8 core.

    However, functionally they behave very similarly.

    Alan

  • Thank you Alan for Your help ,
    I have one more question regarding it ,

    I am also sending some data from dsp to A8 core , but A8 is not able to read it properly , if i am setting a value from dsp A8 is not able to read it ..

    Regards
    Ammar
  • Ammar,

    Ordinarily, once a thread has been marked "Answered" you should open a new thread to address new issues to guarantee that whoever is on Forum duty notices the new question.

    From what you described, either the DSP isn't flushing the data buffer after it writes to it, or the A8 core is not invaliding (ie with Cache_inv() ) the buffer after every read to ensure the cache is filled with new data.

    Alan