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AM335x EtherCAT disabling Enhanced Link issue

g.f.
Guru 15520 points
Other Parts Discussed in Thread: AM3357

Hi,

I have question about AM3357 PRU and ISDK.

My customer are using EtherCAT.
They are connecting other vendor Ether PHY(not TI).

They are not using "pr1_mii0_rxlink" and "pr1_mii1_rxlink" of AM3357.
So, they modified source code(tiescbsp.c) of ISDK as follow:
(This modification method was answered at following E2E(I posted))
e2e.ti.com/.../1639254
*******************************************************************
In tiescbsp.c,
in the function bsp_init, before calling bsp_pruss_mdio_init
Set as follow:
//////////////////////////////////////////////////////////////////
mdioParamsInit.enhancedlink_enable = TIESC_MDIO_RX_LINK_DISABLE;
//////////////////////////////////////////////////////////////////
*******************************************************************

But EtherCAT are not communicating. So, we have following questions.
Q1.Are there anything else to modify in ISDK source code to disable enhanced link?
Q2.Is ISDK supporting "enhanced link disable"?

best regards,
g.f.

  • 0
    TI__Guru**** 393215 points
    I will forward this to the ISDK team.
  • 0 in reply to Biser Gatchev-XID
    TI__Expert 7570 points

    Hi g.f.

    >> Q1.Are there anything else to modify in ISDK source code to disable enhanced link?
    This should be sufficient
    >> Q2.Is ISDK supporting "enhanced link disable"?
    Yes

    Let's quickly check a couple other items

    1)Check PRU MDIO for the PHY and link status
    The MDIO registers are standard for the PRU and CPSW. The definitions are in TRM-CPSW section(Ethernet-Subsystem->Ethernet Subsystem Registers->MDIO Registers)

    AM335x PRU-MDIO base address is 0x4a33_2400
    AM437x PRU_MDIO base address is 0x5443_2400

    MDIO alive. - offset = 8h Each of the 32 bits of this register is set if the most recent access to the PHY with address corresponding to the register bit number was acknowledged by the PHY, the bit is reset if the PHY fails to acknowledge the access. Both the user and polling accesses to a PHY will cause the corresponding alive bit to be updated. The alive bits are only meant to be used to give an indication of the presence or not of a PHY with the corresponding address. Check to see if the expected bits are set.

    MDIO_LINK - offset = Ch This register is updated after a read of the Generic Status Register of a PHY. The bit is set if the PHY with the corresponding address has link and the PHY acknowledges the read transaction. The bit is reset if the PHY indicates it does not have link or fails to acknowledge the read transaction. Check to see if the expected bits are set. 

    2) Check the Phy Status
    The MDIO module includes a user access register (MDIOUSERACCESSn) to directly access a specified Phy. This is described in the MDIO sections for Reading and Writing Data from/to a PHY Register

    3) Check frame and error counters
    Check the vendor protocol specific registers
    For Ethercat check the error indications described in the PRU ICSS EtherCAT firmware API guide at processors.wiki.ti.com/.../PRU_ICSS_EtherCAT_firmware_API_guide

    For Standard Ethernet, Ethernetip , Profinet, and HSR / PRP refer to the ICSS EMAC LLD debug guide at processors.wiki.ti.com/.../ICSS_EMAC_LLD_debug_guide

    David