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Asynchronous signals (AREn ACEn & AOEn ) become inactive after transferring first element by EDMA when using FS=1;

Shehzad
Intellectual 320 points


 I have interfaced a FPGA with DSK6416 by using a ASRAM interfacing technique. When transferring data from EDMA configured as 

EDMA_Config myConfig1 = {
0x21200001, // Frame Synchronized 1D-to-1D Transfer
0xA0000000, // Source address (Asynchronous Memory - FPGA)
0x00020004, // No of frame for transfer(16 bit)-1 || No of element per frame
0x80000000, // Destination address (On board SDRAM)
0x00000000, // Offset after frame
0x00040000 // rld
};

EDMA_config(hEdma1,&myConfig1); // Configure EDMA with parameter of myConfig1

EDMA_enableChannel(hEdma1); // Generating interrupt EER

The read enable signal goes high only for first time then it become inactive? What could be the issue?

  • 0
    TI__Mastermind 35645 points
    Hi,

    We will work on this and let you know the update shortly.

    Thanks & regards,
    Sivaraj K
  • 0 in reply to Sivaraj Kuppuraj
    TI__Mastermind 35645 points

    Hi,

    The latest CSL can be downloaded here:

    http://focus.ti.com/docs/toolsw/folders/print/sprc090.html

    The 6713 CSL EDMA examples included in the above should be very similar for DSK6416 .  One key thing you would need to change is in the build options.  You should see a define in the build options for CHIP_6713 in those examples which you would need to change to CHIP_6416. With this change, the examples would be applicable to 6416 too.

    Kindly try the above CSL EDMA examples from 6713 which would be applicable for 6416 as well except for the change in the build option mentioned above.

    Thanks & regards,

    Sivaraj K

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  • 0
    TI__Guru* 84110 points
    Shehzad,

    Have you tried reading from this source address using the DSP? In particular, try a test with reading from a long long pointer, such as

    volatile long long *p = (long long *)0xA0000000;
    volatile long long var1, var2;

    var1 = *p++;
    var2 = *p++;
    *p = var1+var2;

    It would be good to see what the traces look like for this case, also.

    The problem you are seeing is more likely related to the EMIF configuration than to the EDMA operation. You will want to carefully examine the EMIF Configuration registers. Also, look at the EMA_WAIT signal.

    [FYI, I am used to an active low signal like AREn being called inactive when it is high and active when it is low. This confused me when I read your title and then looked at the picture. Or else there is more to the right of the picture that I cannot see, past tick 70. Just saying.]

    Regards,
    RandyP