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AM1808 Timer : Requesting 32bit Unchained mode example code

user4548196
Prodigy 30 points
Other Parts Discussed in Thread: OMAPL138

Hi

I want to use eight 32bit unchained timer in my application.

I tried in timer 0.  TIM34 operate well, but TIM12 is in reset . ( TIM12RS in TGCR is 0)

Send me example source code. Thanks.

 The following is  my initial code for Timer0  TIM12 and TIM34.

=====================================================

 TimerIntDisable(SOC_TMR_0_REGS, TMR_INT_TMR12_NON_CAPT_MODE | TMR_INT_TMR34_NON_CAPT_MODE);
 TimerDisable(SOC_TMR_0_REGS, TMR_TIMER12 | TMR_TIMER34); //TIMER stop.
 HWREG(SOC_TMR_0_REGS + TMR_TIM12) = 0x0;
 HWREG(SOC_TMR_0_REGS + TMR_TIM34) = 0x0; //timer counter reset
 period=TIMER64P0_34_TIMER_1US_CNT*1000*1000;
 Timer64P23TIM34SetUp32Bit(SOC_TMR_0_REGS,TIMER64P0_PSC34_DIVISOR-1,period);
 IntrChannelMap(SYS_INT_TINT34_0,TIMERP0_34_IRQ_CH,Timer64P0_34Isr);
// TimerIntEnable(SOC_TMR_3_REGS, TMR_INT_TMR34_NON_CAPT_MODE);
// TimerEnable(SOC_TMR_3_REGS, TMR_TIMER34, TMR_ENABLE_CONT); //TIMER start.

 TimerIntDisable(SOC_TMR_0_REGS, TMR_INT_TMR12_NON_CAPT_MODE);
 TimerDisable(SOC_TMR_0_REGS, TMR_TIMER12); //TIMER stop.
 HWREG(SOC_TMR_0_REGS + TMR_TIM12) = 0x0; //timer counter reset
 period=TIMER64P0_12_TIMER_1US_CNT*1000*1000;

    TimerConfigure(SOC_TMR_0_REGS, TMR_CFG_32BIT_UNCH_CLK_BOTH_INT ); //
    TimerPeriodSet(SOC_TMR_0_REGS, TMR_TIMER12, period);
   IntrChannelMap(SYS_INT_TINT12_0,TIMERP0_12_IRQ_CH,Timer64P0_12Isr);

  

  • 0
    TI__Mastermind 43955 points
    Hi user,

    I would recommend you to have a look at the code snippet which configures the timer12 in 32 bit unchained mode.

    It is part of the starterware package, OMAPL138 version 1.10.04.01. File names are Sysdelay.c and Timer.c

    void SysDelayTimerSetup(void)
    {

    /* Configuration of Timer */
    TimerConfigure(SOC_TMR_0_REGS, TMR_CFG_32BIT_UNCH_CLK_BOTH_INT);

    /* Set up the AINTC to generate Timer2 interrupts */
    AintcTimerIntrSetUp();

    /* Enable the timer interrupt */
    TimerIntEnable(SOC_TMR_0_REGS, TMR_INT_TMR12_NON_CAPT_MODE);

    }