C6746 Deep Sleep current drain

Cesar Aguilar

In the application I am working with (single C6746), the current drain was measured at 50mA during deep sleep. In previous applications using a C55, the same current was measured at 25mA. My questions are:

1- Is the C6746 expected to have a current similar drain as the C55 during deep sleep?

2- Do you have information about this expected current drain/power during deep sleep mode for the C6746?

Thanks

over 9 years ago

0 Senthilkumar Srinivasan over 9 years ago

TI__Mastermind 43660 points

Cesar,

The C6746 is from different family and the internal architecture is different between C6746 and C55 devices. The below wiki page would be helpful to understand the device condition in deep sleep mode.

processors.wiki.ti.com/.../42_Power_Consumption_Summary

Regards,
Senthil

0 Cesar Aguilar over 9 years ago in reply to Senthilkumar Srinivasan

Prodigy 230 points

Senthil,
Thank you for the information. Another question: I followed the procedure to power down the PLL controllers right before entering deep sleep. 1- Do I have to shutdown any other peripherals to avoid current drain?
2- Do GPIOs have to be put in any particular state before entering deep sleep to avoid current drain?
Thanks
Cesar

0 Senthilkumar Srinivasan over 9 years ago in reply to Cesar Aguilar

TI__Mastermind 43660 points

Cesar,

I believe you followed the procedure described in section 9.9 Deep Sleep Mode in device TRM. If you are following this, there is no additional requirement to achieve deep sleep. On deep sleep mode, the device would consume baseline leakage power only. Please refer power consumption spreadsheet in the wiki page that i mentioned in the above post.

Regards,
Senthil

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C6746 Deep Sleep current drain