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U-boot errors on custom AM5K2E04 board. Using U-boot K2E EVM config. URGENT

Samuel Smith
Intellectual 300 points
Other Parts Discussed in Thread: AM5K2E04, 66AK2E05

TI Team,

My team has built a custom board using the AM5K2E04 SoC. We are trying to get u-boot working using the k2e_evm_config as a start, but we have a few different peripherals than the TI K2E EVM board. Right now, we get to a prompt, but most things aren't fully functional. Ethernet initializes, but doesn't connect. SPI identifies the N25Q128A, but cannot read it. NAND throws errors when trying to write to it.

We want to know how to fix these issues and get Ethernet, NAND, SPI, and our VxWorks 7 OS working correctly.

Our board status:

  1. XDS200 fails to reset the processor (using the 66AK2E05 gel file) so we abandoned using it.
  2. It doesn't have a BMC.
  3. SPI flash and NAND are empty.
  4. UART works.
  5. Ethernet connections have green LEDs.
  6. We can change the boot mode using the FPGA to edit the DEVSTAT register.

Our u-boot build process so far:

  1. Downloaded latest keystone-linux u-boot, with latest cross-compiler.
  2. make k2e_evm_config
  3. Edited the ddr3 registers config, ddr3 spd logic, and ks2_evm.h variables.
  4. Built u-boot.bin
  5. Padded u-boot.bin to make u-boot.uart (so the start was at 0x0c001000)
  6. Booted board in UART mode
  7. Used Teraterm to XMODEM over the u-boot.uart BLOB.
  8. U-boot gets to a prompt.

HW changes between our custom AM5K2E04 board and the K2E EVM:

  • ETH: 2 Ethernet ports start at PHY address 8, instead of 0. Using M88E1145 (Marvel) device, instead of M88E1111.
  • SPI: Micron (St Micro) N25Q128A device
  • NAND: Micron MT29F16G08ADBC device (2 GB)
  • DDR3: 8 banks of 512MB (total 4 GB) starts at 0x08 0000 0000.

Error Symptoms:

  • VxWorks 7 crashes almost immediately (at an MCR p15 assembly call to enable MMU)
  • Ethernet LEDs are on, but pings and tftp timeout.
  • 'sf probe' returns correct part name, but 'sf read' doesn't return anything.
  • NAND writes throw an error: 'MTD Erase failure: -5'

Every register we check is set up as expected. Looking for help.

- Samuel Smith, Northrop Grumman Team

  • 0
    TI__Mastermind 43955 points

    Hi Samuel Smith,

    Please use our platform test code to test the NAND and SPI flash on your target board.

    Latest MCSDK package:

    C:\ti\pdk_keystone2_3_01_04_07\packages\ti\platform\evmk2e\platform_test

    Latest processor SDK package:

    C:\ti\pdk_k2e_4_0_0\packages\ti\platform\evmk2e\platform_test

    You can also test the SPI flash on u-boot shell.

    You should get different data after copied to  0x88000000 RAM locations.

    u-boot#  sf probe

    u-boot#  md.l 0x88000000

    u-boot#  sf read 0x88000000 0x0 0x1000

    u-boot#  md.l 0x88000000

  • 0
    TI__Guru** 116100 points
    In addition to Shankari suggestions, I want to add up.
    Have you modified the u-boot configuration file for your HW change ?
    Yes, you have modified DDR, how about SPI, NAND flash etc., ?
    Is there any HW change in SPI and Nand flash (like CS, WAIT etc.,) ?

    Can you try to ping any IP address from u-boot shell?
    Sorry, we are not sure about Vxworks. Please do check with windriver


    NAND writes throw an error: 'MTD Erase failure: -5'

    Where did you try this ?
    u-boot or Vxworks ??

    As Shankari pointed out, you can try the platform test code to test the NAND and SPI flash.

    Also you can try NDK examples on your board.
    C:\ti\mcsdk_bios_3_01_04_07\examples\ndk

    From this test projects, you can confirm that you don't have any HW issue.
  • 0 in reply to Shankari G
    Intellectual 300 points

    Here is the console output from those commands: I think maybe the 'sf write' i did put all f's in the memory.

    U-Boot 2013.01-ge9a0093-dirty (Mar 23 2016 - 18:47:25)

    I2C:   ready
    Skipping get_dimm_params_from_spd
    Detected SO-DIMM []
    DDR3 speed 201340177
    DRAM: 4 GiB

    Reseting entire DDR3 memory to 0 ...
    DRAM:  512 MiB
    NAND:  2048 MiB
    Using default environment

    In:    serial
    Out:   serial
    Err:   serial
    Smart Reflex Class 0 temperature compensation enabled
    tps544_init i2c write error
    Smart Reflex Class 0 temperature compensation disabled
    Net:   K2E_EMAC0
    Warning: K2E_EMAC0 using MAC address from net device
    , K2E_EMAC1, K2E_EMAC2, K2E_EMAC3
    K2E EVM # sf probe
    SF: Detected N25Q128A with page size 64 KiB, total 16 MiB
    K2E EVM # md.l 0x88000000
    88000000: 00000000 00000000 00000000 00000000    ................
    88000010: 00000000 00000000 00000000 00000000    ................
    88000020: 00000000 00000000 00000000 00000000    ................
    88000030: 00000000 00000000 00000000 00000000    ................
    88000040: 00000000 00000000 00000000 00000000    ................
    88000050: 00000000 00000000 00000000 00000000    ................
    88000060: 00000000 00000000 00000000 00000000    ................
    88000070: 00000000 00000000 00000000 00000000    ................
    88000080: 00000000 00000000 00000000 00000000    ................
    88000090: 00000000 00000000 00000000 00000000    ................
    880000a0: 00000000 00000000 00000000 00000000    ................
    880000b0: 00000000 00000000 00000000 00000000    ................
    880000c0: 00000000 00000000 00000000 00000000    ................
    880000d0: 00000000 00000000 00000000 00000000    ................
    880000e0: 00000000 00000000 00000000 00000000    ................
    880000f0: 00000000 00000000 00000000 00000000    ................
    K2E EVM # sf read 0x88000000 0x0 0x1000
    K2E EVM # md.l 0x88000000
    88000000: ffffffff ffffffff ffffffff ffffffff    ................
    88000010: ffffffff ffffffff ffffffff ffffffff    ................
    88000020: ffffffff ffffffff ffffffff ffffffff    ................
    88000030: ffffffff ffffffff ffffffff ffffffff    ................
    88000040: ffffffff ffffffff ffffffff ffffffff    ................
    88000050: ffffffff ffffffff ffffffff ffffffff    ................
    88000060: ffffffff ffffffff ffffffff ffffffff    ................
    88000070: ffffffff ffffffff ffffffff ffffffff    ................
    88000080: ffffffff ffffffff ffffffff ffffffff    ................
    88000090: ffffffff ffffffff ffffffff ffffffff    ................
    880000a0: ffffffff ffffffff ffffffff ffffffff    ................
    880000b0: ffffffff ffffffff ffffffff ffffffff    ................
    880000c0: ffffffff ffffffff ffffffff ffffffff    ................
    880000d0: ffffffff ffffffff ffffffff ffffffff    ................
    880000e0: ffffffff ffffffff ffffffff ffffffff    ................
    880000f0: ffffffff ffffffff ffffffff ffffffff    ................
    K2E EVM #

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points
    We modified these files so far:
    * include/configs/ks2_evm.h - changed NR_DRAM_BANKS, MAX_RAM_BANK_SIZE, removed ETH_PHY_MARVEL_88E1111, and added env variables: ipaddr, netmask, serverip, and ddr3a_size
    * board/ti/ks2_evm/ddr3_cfg.c for the registers
    * board/ti/ks2_evm/ddr3_k2e.c for the spd logic
    * board/ti/ks2_evm/board_k2e.c for the phy_addr on the emac ports.

    We found the ddr3 register cfg file easily. Where are the cfg files for our NAND and SPI?
    Yes, there are hardware changes for the NAND, but not for the SPI. I listed the new parts in first post. The Chip Select for NAND stumps me a bit because the default is '2', i thought it should be '0' but the logic that uses it subtracts 2 immediately.

    That NAND error was in response to a 'saveenv' command in u-boot:

    K2E EVM # saveenv
    Saving Environment to NAND...
    Erasing Nand...
    nand_bbt: ECC error while reading bad block table
    nand_erase_nand: attempt to erase a bad block at page 0x0007ffc0
    nand_bbt: Error while writing bad block table -5
    Timeout!
    nand0: MTD Erase failure: -5

    Writing to Nand... Timeout!FAILED!
    K2E EVM #
  • 0 in reply to Shankari G
    Intellectual 300 points
    How do I run the platform test code? I would need more detailed instructions. I have that version of the pdk installed.
  • 0 in reply to Samuel Smith
    Intellectual 300 points
    Okay, 2 updates:
    We figured out how to run the platform test.
    And we confirmed that "sf write" is working as expected. But when I try to boot from SPI, it is reading the SPI data correctly (our scope saw the correct bits on the wire) but failing to boot successfully. Both for the 'u-boot-spi.gph' and the 'u-boot.bin' that was formatted for spi using 'fmtimg'.
  • 0 in reply to Samuel Smith
    Intellectual 300 points
    The platform_test from 'C:\ti\pdk_keystone2_3_01_04_07\packages\ti\platform\evmk2e\platform_test' unmodified, prints nothing when run.
  • 0 in reply to Samuel Smith
    Intellectual 300 points
    Update:
    * Ethernet still doesn't work.
    * I can read NAND, but writes and erases fail.
    * OS still dies early on.
    * SPI Flash boot does work. My mistake. DEVSTAT register was slightly off.

    Ideas we had:

    * The SerDes clock for the SGMII is 125 Mhz on our custom board, while the eval board has 156.25 MHz. We would like to know what changes at the SerDes control registers (at 0x0232a000) need to be made. (The rate is the same: 5G.) The file that these are set in is drivers/net/keystone_serdes.c
    * The logic in 'keystone_sgmii_config'. in file drivers/net/keystone_net.c, behaves very differently from the logic in the Post Test for Emac at 'init_sgmii'. in file 'arch/arm/cpu/armv7/keystone/post.c'. We like the way init_sgmii sets the registers, but it still doesn't work.
    * The biggest difference between our board and the K2E EVM Ethernet device is that our Port '0' has PHY Address '8'. We haven't found any code that seems to mind, but it's a difference.
  • 0 in reply to Samuel Smith
    TI__Guru** 116100 points
    Dear Samuel,

    And we confirmed that "sf write" is working as expected. But when I try to boot from SPI, it is reading the SPI data correctly (our scope saw the correct bits on the wire) but failing to boot successfully. Both for the 'u-boot-spi.gph' and the 'u-boot.bin' that was formatted for spi using 'fmtimg'.

    It seems SPI HW connection is good. We can check the SPI boot later since we don't workable u-boot binary as need changes on NAND, Ethernet etc., so it may need some changes for successful boot.

    SPI flash method:
    1) Booted and got u-boot prompt from NAND or CCS.
    2) And here is the step to update the u-boot on SPI.
    tftpboot 0x88000000 u-boot-spi.gph
    sf probe
    sf erase 0 0x100000
    sf write 0x88000000 0 0x100000


    The platform_test from 'C:\ti\pdk_keystone2_3_01_04_07\packages\ti\platform\evmk2e\platform_test' unmodified, prints nothing when run.

    You will get the output logs on UART.
    I would like you to suggest to try first on EVM board then try it on your custom target board.


    * Ethernet still doesn't work.
    * I can read NAND, but writes and erases fail.

    Are you trying this with platform test code ?
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points

    Titusrathinaraj Stalin said:

    The platform_test from 'C:\ti\pdk_keystone2_3_01_04_07\packages\ti\platform\evmk2e\platform_test' unmodified, prints nothing when run.


    You will get the output logs on UART.
    I would like you to suggest to try first on EVM board then try it on your custom target board.

    I do not currently have a K2E EVM to test the platform code on. I am only using my u-boot shell. All tests you ask of me need to be run on our board.

    Titusrathinaraj Stalin said:

    * Ethernet still doesn't work.
    * I can read NAND, but writes and erases fail.


    Are you trying this with platform test code ?

    Ethernet is failing in u-boot. The LEDs are on, but no packages can be sent or received.

    NAND writes are failing in u-boot.

    Now I mentioned that there are 2 hardware discrepancies regarding Ethernet: 

    1. the SerDes clock is running at 125 instead of 156.25, so I believe those registers need to be edited.
    2. We are using the Marvell 88E1145 part, while the EVM seems to use the 88E1111, with support for the 88E1145. I'm not sure how it's actually setting registers related to this hardware, and need help figuring this out.

  • 0 in reply to Samuel Smith
    TI__Guru** 116100 points

    the SerDes clock is running at 125 instead of 156.25, so I believe those registers need to be edited.
    We are using the Marvell 88E1145 part, while the EVM seems to use the 88E1111, with support for the 88E1145. I'm not sure how it's actually setting registers related to this hardware, and need help figuring this out.

    You have to modify the below files.

    sgmii_serdes_setup_156p25mhz
    TO
    sgmii_serdes_setup_125mhz

    You have to write a function "sgmii_serdes_setup_125mhz" with SERDES values.

    ./arch/arm/include/asm/arch-keystone/hardware.h
    ./drivers/net/keystone_net.c

    Please refer to the following file for reference.
    ~ti/pdk_keystone2_3_01_04_07/packages/ti/platform/evmk2e/platform_lib/src/evmc66x_phy.c

    void CSL_SgmiiDefSerdesSetup()
    serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;

    ./csl/src/ip/serdes_sb/V0/csl_serdes.h

    /** @addtogroup CSL_SERDES
    @{ */
    /** ============================================================================
    * @n@b CSL_SERDES_REF_CLOCK
    *
    * @brief
    *
    *
    * SERDES REF CLOCK speed enumerators */
    typedef enum
    {
    /** 100 MHz */
    CSL_SERDES_REF_CLOCK_100M = 0,

    /** 122.8 MHz */
    CSL_SERDES_REF_CLOCK_122p88M = 1,

    /** 125 MHz */
    CSL_SERDES_REF_CLOCK_125M = 2,

    /** 153.6 MHz */
    CSL_SERDES_REF_CLOCK_153p6M = 3,

    /** 156.25 MHz */
    CSL_SERDES_REF_CLOCK_156p25M = 4,

    /** 312.5 MHz */
    CSL_SERDES_REF_CLOCK_312p5M = 5
    } CSL_SERDES_REF_CLOCK;


    /** ============================================================================
    * @brief
    *
    * SERDES LINK RATE speed enumerators */
    typedef enum
    {
    /** 1.25 Gpbs */
    CSL_SERDES_LINK_RATE_1p25G = 0,

    /** 3.125 Gbps */
    CSL_SERDES_LINK_RATE_3p125G = 1,

    /** 4.9152 Gbps */
    CSL_SERDES_LINK_RATE_4p9152G = 2,

    /** 5 Gbps */
    CSL_SERDES_LINK_RATE_5G = 3,

    /** 6.144 Gbps */
    CSL_SERDES_LINK_RATE_6p144G = 4,

    /** 6.25 Gbps */
    CSL_SERDES_LINK_RATE_6p25G = 5,

    /** 7.3728 Gbps */
    CSL_SERDES_LINK_RATE_7p3728G = 6,

    /** 9.8304 Gbps */
    CSL_SERDES_LINK_RATE_9p8304G = 7,

    /** 10 Gbps */
    CSL_SERDES_LINK_RATE_10G = 8,

    /** 10.3125 Gbps */
    CSL_SERDES_LINK_RATE_10p3125G = 9,

    /** 12.5 Gbps */
    CSL_SERDES_LINK_RATE_12p5G = 10
    } CSL_SERDES_LINK_RATE;
  • 0 in reply to Titusrathinaraj Stalin
    TI__Guru** 116100 points

    Dear Samuel,

    Sorry for the delayed response, forgot to answer rest of the questions as I didn't get any notification for this post.

    I think, you are facing issues with NAND and Ethernet now and SPI issue was got fixed.
    Have you tried to modify the ethernet configuration as I given in the above post ?


    Yes, there are hardware changes for the NAND, but not for the SPI. I listed the new parts in first post. The Chip Select for NAND stumps me a bit because the default is '2', i thought it should be '0' but the logic that uses it subtracts 2 immediately.

    That NAND error was in response to a 'saveenv' command in u-boot:

    K2E EVM # saveenv
    Saving Environment to NAND...
    Erasing Nand...
    nand_bbt: ECC error while reading bad block table
    nand_erase_nand: attempt to erase a bad block at page 0x0007ffc0
    nand_bbt: Error while writing bad block table -5
    Timeout!
    nand0: MTD Erase failure: -5

    Writing to Nand... Timeout!FAILED!
    K2E EVM #


    NAND flash used : NAND: Micron MT29F16G08ADBC device (2 GB) (2 die)
    K2E EVM used : MT29F4G08ABBDAH4D (as per the schematics) (1 die)

    No of die is the only difference.
    K2E EVM uses CS0 and WAIT0 pins, how about yours ?

    Also, we have NAND writer project, can you please try and let me know how it goes for this custom board.
    C:\ti\mcsdk_bios_3_01_04_07\tools\writer\nand\evmk2e

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points

    Titusrathinaraj Stalin said:

    the SerDes clock is running at 125 instead of 156.25, so I believe those registers need to be edited.
    We are using the Marvell 88E1145 part, while the EVM seems to use the 88E1111, with support for the 88E1145. I'm not sure how it's actually setting registers related to this hardware, and need help figuring this out.


    You have to modify the below files.

    sgmii_serdes_setup_156p25mhz
    TO
    sgmii_serdes_setup_125mhz

    You have to write a function "sgmii_serdes_setup_125mhz" with SERDES values.

    ./arch/arm/include/asm/arch-keystone/hardware.h
    ./drivers/net/keystone_net.c

    Please refer to the following file for reference.
    ~ti/pdk_keystone2_3_01_04_07/packages/ti/platform/evmk2e/platform_lib/src/evmc66x_phy.c

    void CSL_SgmiiDefSerdesSetup()
    serdes_lane_enable_params1.ref_clock = CSL_SERDES_REF_CLOCK_156p25M;

    ./csl/src/ip/serdes_sb/V0/csl_serdes.h

    What you suggested may work, but I was able to solve my Ethernet - SerDes register problem using information from the ticket: https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/501793

    I edited the registers in ../drivers/net/keystone_serdes.c to the same registers that are set in the ~/ti/pdk_keystone2_3_01_04_07/packages/ti/csl/src/ip/serdes_sb/V0/csl_wiz8_sb_refclk125MHz_10bit_5Gbps.c file.

    Now on to NAND.

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points

    Titusrathinaraj Stalin said:


    NAND flash used : NAND: Micron MT29F16G08ADBC device (2 GB) (2 die)
    K2E EVM used : MT29F4G08ABBDAH4D (as per the schematics) (1 die)

    No of die is the only difference.
    K2E EVM uses CS0 and WAIT0 pins, how about yours ?

    Also, we have NAND writer project, can you please try and let me know how it goes for this custom board.
    C:\ti\mcsdk_bios_3_01_04_07\tools\writer\nand\evmk2e

    I will look at this project and see if I can determine how to correct the NAND config in the keystone_linux_u-boot.

  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points

    Titusrathinaraj Stalin said:


    NAND flash used : NAND: Micron MT29F16G08ADBC device (2 GB) (2 die)
    K2E EVM used : MT29F4G08ABBDAH4D (as per the schematics) (1 die)

    No of die is the only difference.
    K2E EVM uses CS0 and WAIT0 pins, how about yours ?

    Also, we have NAND writer project, can you please try and let me know how it goes for this custom board.
    C:\ti\mcsdk_bios_3_01_04_07\tools\writer\nand\evmk2e

    Understood about the Die. We are using CS0, but we are WAIT1, not WAIT0. How do I change this in u-boot?

  • 0 in reply to Samuel Smith
    Intellectual 300 points
    Another NAND difference is we are 8bit ECC with a OOB of 224, and the K2E is 4bit ECC and 64 OOB. We need to change this in the code, but I don't see any code in the ./devoces/nand folder that has support for that setup.
  • 0 in reply to Samuel Smith
    TI__Guru** 116100 points
    Dear Samuel,

    Another NAND difference is we are 8bit ECC with a OOB of 224, and the K2E is 4bit ECC and 64 OOB. We need to change this in the code, but I don't see any code in the ./devoces/nand folder that has support for that setup.

    You can get the NAND OOB and ECC layout information in "drivers/mtd/nand/davinci_nand.c" file.


    Understood about the Die. We are using CS0, but we are WAIT1, not WAIT0. How do I change this in u-boot?

    Is it possible to use the WAIT0 in HW ?

    I have seen the similar problem in other post.
    e2e.ti.com/.../1769054
    e2e.ti.com/.../1823800
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points
    We are able to change the WAIT by setting the AWCR register in SW. U-boot is setting it to WAIT0 by default. Us changing it to WAIT1 didn't fix the NAND reads and writes.

    In response to the ECC and OOB differences, we looked in davinci_nand.c, and there is only support there for 4bit ECC. Where is code in the PDK or MCSDK that initializes NAND with 8bit ECC and 224 OOB? I want to see working code so I can copy it for u-boot.

    Our HW is 8bit ECC. The Keystone2 EMIF document (sprugz3a) does not list 8bit ECC support. Only 4bit ECC support.
    Will our processor (66AK2E) even support the NAND part we chose? (Micron MT29F16G08ADBC device)





    Also I want to describe the behavior of the NAND read and write commands:
    1. 'nand read ...' only reads out 'ffffffff's.
    2. Before running any commands, the NAND memory start address displays the READID repeatedly:
    30000000: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...
    30000010: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...
    30000020: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...
    30000030: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...
    3. After trying to do a 'nand erase ...' or 'nand write ...' to any location, the NAND memory changes to 'e0e0e0e0' repeated. And this error prints in u-boot:

    66AK2E BOARD # nand erase 0 10

    NAND erase: device 0 offset 0x0, size 0x10
    nand_bbt: ECC error while reading bad block table
    nand_erase_nand: attempt to erase a bad block at page 0x0007ffc0
    nand_bbt: Error while writing bad block table -5
    Timeout!
    nand0: MTD Erase failure: -5

    OK
  • 0 in reply to Samuel Smith
    TI__Guru** 116100 points
    Dear Samuel,

    Your NAND part seems to be 4K page size, have you modified it for 4K in config file ?
    include/configs/k2e_evm.h
    #define CONFIG_SYS_NAND_PAGE_4K

    Can you please refer to the following e2e post ?
    This post similar to our problem.
    e2e.ti.com/.../732876

    Also please refer to the following TI wiki page.
    processors.wiki.ti.com/.../Raw_NAND_ECC
    processors.wiki.ti.com/.../Raw_NAND_ECC


    2. Before running any commands, the NAND memory start address displays the READID repeatedly:
    30000000: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...
    30000010: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...
    30000020: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...
    30000030: 26d1a52c 00000068 26d1a52c 00000068 ,..&h...,..&h...

    This looks like, its printing the NAND CHIP ID and FULL ID...
    I have seen similar observation (printing NAND ID) in multi die flash devices.
    So, also check with micron for that....
  • 0 in reply to Titusrathinaraj Stalin
    TI__Guru** 116100 points
    Dear Samuel,
    If still you are facing issue, you can try to patch the u-boot to support 8bit ECC in SW.

    Please refer to the below post.
    e2e.ti.com/.../732876

    Please let me know how it goes.
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points
    TI,
    I jumped from NAND to work on PCIe support on my board.
    I was able to get u-boot to initialize PCIe support by using the process detailed in 'C:\ti\pdk_keystone2_3_01_04_07\packages\exampleProjects\PCIE_K2EC66BiosExampleProject'.
  • 0 in reply to Samuel Smith
    Intellectual 300 points
    Also, I am having an issue with TFTP transfer from my host which is directly connected to the board.
    When I run the command 'tftp <addr> <file>' for a small file (<200K), it works just fine.

    Board # tftp c000000 u-boot.bin
    Using EMAC0 device
    TFTP from server 192.168.20.200; our IP address is 192.168.20.199
    Filename 'u-boot.bin'.
    Load address: 0xc000000
    Loading: T #################################################################
    ######
    58.6 KiB/s
    done
    Bytes transferred = 359324 (57b9c hex)
    Board #

    But, when I run tftp for a large file (>1MB), the tftp transfer occurs, but at the end it just keeps timing out and never successfully exits back to the shell. I have to use 'Ctrl + C' to get back to a shell.

    Board # tftp 80100000 vxWorks.bin
    Using EMAC0 device
    TFTP from server 192.168.20.200; our IP address is 192.168.20.199
    Filename 'vxWorks.bin'.
    Load address: 0x80100000
    Loading: T #################################################################
    #################################################################
    #################################################################
    #################################################################
    #################################################################
    ################################################################T T T T T T T T T T T T T ...

    The tftp server says that the transfer completed, but u-boot doesn't stop and go back to a shell. I have to manually 'Ctrl + C' out.
    Why could this be happening?

    -Sam
  • 0 in reply to Samuel Smith
    TI__Guru** 116100 points
    Dear Samuel,
    I think, your NAND may work if you connect the WAIT0 pin to flash instead of WAIT1 pin in hardware.

    I have seen one customer who is able to read & write his custom 8bit ECC NAND with 4bit ECC SW configuration.

    Please refer to the following discussion.
    e2e.ti.com/.../1826502

    Also please let us know if any problem with PCIe.
    It would be good if you create a new post for the followup question in PCIe if any.

    Thanks for your understanding.
  • 0 in reply to Titusrathinaraj Stalin
    Intellectual 300 points
    NAND is working now. The WAIT pin didn't have a pull-up, so we had to fix the hardware.

    On to PCIe!
  • 0 in reply to Samuel Smith
    TI__Guru** 116100 points
    Dear Samuel,
    Sounds good.
    Thanks for the update.

    BTW, which WAIT pin was used ? WAIT0 or WAIT1 ?