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VLYNQ slave device boot

Zorg
Prodigy 210 points

Hi.
I am trying to run the Slave device (DM6437) from the Master's (DM6437)
From the Master device with NOR (0x42000000) copy the image to the Slave device DDR2 at 0x87000000
through VLYNQ, ie I see that the data is actually written to me on the desired address in the Slave device
but after recording:
* RemoveDSPBOOTADDR = 0x87000000;
* RemoveBOOTCMPLT | = 0x1;
launch fails.
Written test on the Master device: copy the same image of NOR (0x42000000) -> DDR2 (0x87000000)
and do:
CFG_DSPBOOTADDR = 0x87000000;
CFG_BOOTCMPLT | = 0x1;
launch fails.
But if I do this:
void (* application) (void);
application = (void (*) (void)) ((Uint32 *) 0x87000000);
(* Application) ();
the code starts.
P.S. The image that I copy from NOR and has asm code to download, checking work and blinking LED.
DDR2 from the Slave is set in accordance with the gel file.
How to run the image on the Slave device through VLYNQ ???

  • 0
    TI__Mastermind 35645 points
    Hi,

    We are working on this and will get back to you shortly.

    Thanks & regards,
    Sivaraj K
  • 0 in reply to Sivaraj Kuppuraj
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    The VLYNQ master would directly load the code into the memory of the VLYNQ slave.  It is very similar to the HPI boot mode. If you want to use the VLYNQ boot mode then you would need to write a bootloader that runs on the VLYNQ master to write the code to the appropriate memory addresses on the slave that you're trying to boot.

    The ROM bootloader supports boot via VLYNQ with DSP as VLYNQ slave. The bootloader ensures that VLYNQ is enabled and then polls for BOOTCMPLT.CMPLT flag in the BOOTCMPLT register to indicate that the download of application by VLYNQ Host is complete. The bootloader will then branch to the start address in DSPBOOTADDR as written by the VLYNQ Host. The boot process for VLYNQ then is as follows:

    1. If FASTBOOT is enabled bootloader configures PLL according using appropriate PLL multiplier.

    2. Bootloader makes sure VLYNQ is enabled.

    3. Bootloader executes empty loop polling for BOOTCMPLT.CMPLT flag.

    4. VLYNQ Host downloads application to DSP.

    5. VLYNQ Host writes application start address to DSPBOOTADDR register.

    6. VLYNQ Host writes 1 to BOOTMCPLT.CMPLT register flag.

    7. Bootloader detects BOOTCMPLT.CMPLT and branches to start address in DSPBOOTADDR.

    For more details, please see the doc. below:

    http://www.ti.com.cn/cn/lit/an/spraag0e/spraag0e.pdf

    Thanks & regards,

    Sivaraj K

    -------------------------------------------------------------------------------------------------------

    Please click the Verify Answer button on this post if it answers your question

    -------------------------------------------------------------------------------------------------------

  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 210 points
    Hi.
    Thank you for your reply.
    It is in this sequence and carried out all but the launch did not occur.

    These are my steps:
    1. SLAVE DSP exhibition FASTBOOT = 1, BOOTMODE [3: 0] = 1010b
    2. The connection between the DSP and the MASTER DSP SLAVE VLYNQ for 4-wire (TX_MASTER [0: 3] -> RX_SLAVE [0: 3], TX_SLAVE [0: 3] -> RX_MASTER [0: 3], SCRUN_MASTER-> SCRUN_SLAVE, CLOCK_VLYNQ_MASTER = CLOCK_VLYNQ_SLAVE = EXTERNAL_27_MHZ)
    3. Launch DSP MASTER FASTBOOT = 1, BOOTMODE [3: 0] = 0100b, pour through the CCS firmware MASTER_BOOT
    4. Initializing VLYNQ, and desired regions I,
    - LOC_0x4C000000 = REM_0x87000000 len 0x00080000 (firmware space DDR2)
    - LOC_0x4C080000 = REM_0x01800000 len 0x00800000 (CFG_space + CFG_peripherals)
    - LOC_0x4C880000 = REM_0x20000000 len 0x00008000 (DDR_Controler)
    5. Initializing SLAVE_ DDR2
    6. MASTER_BOOT copies with MASTER_NOR (0x42000000) -> SLAVE_DDR2 (0x87000000) image to download (.boot_load + DSP / BIOS)
    7. Checking the data are MASTER_NOR [0x42000000-0x42080000] = SLAVE_DDR2 [0x87000000-0x87080000]
    8. I produce a record SLAVE_DSPBOOTADDR = 0x87000000;
    9. I produce a record SLAVE_BOOTCMPLT | = 0x1;
    10. no reaction.

    P.S.
    1. firmware created using:
    hex6x.exe slave.out
    --motorola
    --image
    --memwidth=8
    --map=slave.map
    --boot
    --bootorg=0x42000080
    --bootsection=.boot_load 0x42000000
    --fill=0xffffffff

    ROMS
    {
    FLASH : org = 0x42000000, len = 0x00080000, romwidth=8, files={slave.hex}
    }

    2. Boot routine (.boot_load):
    ; ======== boot ========
    ;
    .title "Flash bootup utility"
    .option D,T
    .length 102
    .width 140

    ; Address of the generated boot-table 0x87000080
    copyTable .equ 0x87000080

    .sect ".boot_load"
    .global _boot

    _boot:
    ;****************************************************************************
    ; copy sections
    ;****************************************************************************
    mvkl copyTable, a3 ; load table pointer
    mvkh copyTable, a3

    ldw *a3++, b1 ; Load entry point

    copy_section_top:
    ldw *a3++, b0 ; byte count
    ldw *a3++, a4 ; ram start address
    nop 3

    [!b0] b copy_done ; have we copied all sections?
    nop 5

    copy_loop:
    ldb *a3++,b5
    sub b0,1,b0 ; decrement counter
    [ b0] b copy_loop ; setup branch if not done
    [!b0] b copy_section_top
    zero a1
    [!b0] and 3,a3,a1
    stb b5,*a4++
    [!b0] and -4,a3,a5 ; round address up to next multiple of 4
    [ a1] add 4,a5,a3 ; round address up to next multiple of 4

    ;****************************************************************************
    ; jump to entry point
    ;****************************************************************************
    copy_done:
    b .S2 b1
    nop 5
  • 0 in reply to Zorg
    TI__Mastermind 30915 points

    Hi Zorg,

    I would advise to check the different steps one by one in order to identify where the problem lies:

    - In order to check that VLYNQ interface is functionnal check that host and slave can communicate over VLYNQ:
       - Using JTAG are you able to load a test code on both device to test the VLYNQ interface?
       - Can you check this way the master to slave interrupt interrupt mecanism too?
    You could use the VLYNQ PSP driver examples to validate the VLYNQ interface before trying to boot.

    - In order to check that the boot image created is valid:
       - are you able to test AIS boot over an other boot interface like I2C or UART?
       - Can you test with the simpliest possible boot code like a while (1) loop?
       - Can you check that the boot code is able to run on the target you want to boot? (you can load it via JTAG to test the execution)


    - Specifically on VLYNQ boot:
      Do you see any signal or comunication on the VLYNQ port during boot?
      May be you are able to identify what part of the boot code the slave and master are running using the PC register?
      Also you could check using JTAG if the slave VLYNQ module is powered, enabled and if any error flags are set in the VLYNQ registers.


    A.

  • 0
    Prodigy 210 points
    Thank you all for your answers. Everything works as it should. The problem was in the initialization DDR2.