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question about SERDES Implementation Guideline

zhen yang43
Intellectual 340 points


 "A SERDES routing place should be adjacent to a reference plane (either ground or power) and within one signal plane of a ground reference plane". I m from china ,i don't konw it's true meaning,a serdes need one or two reference plane? thank you very much

  • 0
    TI__Guru* 81335 points

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com). Please read all the links below my signature.

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  • 0 in reply to Raja
    TI__Guru**** 182761 points

    Yang

    You need to route the Serdes signals with reference to one solid ground or power plane, although ground plane is preferred. Also, do not route across a split ground plane.

    Thanks

    David 

  • 0 in reply to David (ASIC) Liu
    Intellectual 340 points

    David

           thany you for your reply. your meaning is that the layer which  the serdes signals reside  should refer to two solid plane?or although its adjaceng layer has one solid plane and one split grond plane ,i can make the signal layer with the solid plane tightly coupled.that is the distance between them are shorter? maybe you can paste a  graphic to illustrate.

    thank you very much .

    Yang

  • 0 in reply to zhen yang43
    TI__Guru**** 182761 points

    Yang

    An example stackup is shown below. For signal on layer 1, the reference plane is layer 2, which is a Ground plane. Both layer 4 and 6 user layer 5 as the reference plane.

    Layer Type Description
    1 Signal Top routing
    2 Plane Ground
    3 Plane Split Power
    4 Signal Internal Routing
    5 Plane Ground
    6 Signal Bottom Routing

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Intellectual 340 points

    David 

                layer 4   can't be used to route the serdes signal ?if  i route the serdes signal in the layer 4 ,i want to konw how to use the layer5 for the reference plane instead of   the layer 3 .it depent on the distance between them?

    Thank you very much

    Yang

  • 0 in reply to zhen yang43
    TI__Guru**** 182761 points
    Yang

    Layer 4 can be used to route the Serdes signals. If layer 3 is split power plane and you need to use layer 5 as the reference plane, then yes, you need to shorten the distance between layer 4 and 5 so layer 5 is the dominate plane than layer 3.

    Thanks
    David
  • 0 in reply to David (ASIC) Liu
    Intellectual 340 points

    David

              we know that the serdes signal  has two reference grond is the best  case ,i want to konw in the case that only have one reference ground ,the speed of the signal is limited  to 2.5gbps ,3.125gbps or 10g bps?do you have a simulation to prove ?The signal intefrity is important to me .

    Tank you very much 

    Yang

  • 0 in reply to zhen yang43
    TI__Guru**** 182761 points

    Yang

    I do not understand why you would need two reference ground planes for Serdes signals. For our board design up to 10G, we have always used one reference ground plane as the return path for the Serdes signals.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Intellectual 340 points

    David 

              can you give me a link about a evaluation board' brd file ,my colleague worry that 6.25g serdes signal can' t route  cross a split plane althougth unedr ths signal layer has a solid ground plane .if the serdes signal route in the layer 4,i want to know how much the distance  the layer4 to layer 3 and layer 5.

    Layer Type Description
    1 Signal Top routing
    2 Plane Ground
    3 Plane Split Power
    4 Signal Internal Routing
    5 Plane Ground
    6 Signal Bottom Routing

    Thank you very much 

    Yang

  • 0 in reply to zhen yang43
    TI__Guru**** 182761 points

    Yang

    You can find C6678 EVM layout file with this link: . 

    The distance between layer 4 and layer 3/5 depends on PCB material, trace thickness and width, etc, it needs to be calculated to ensure the differential signal trace on layer 4 maintains 100ohm impedance.

    Thanks

    David

  • 0 in reply to David (ASIC) Liu
    Intellectual 340 points

    David

                 I sincerely appreciate your help.

    Yang