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C5505 ADC System Frequency

Saba Molani
Prodigy 20 points


I am using the TMSC5505EZDSP development kit. I want to set the ADC sampling frequency to 8KHz. In order to do that I need to know the system clock frequency so I can set the clock divisor in the code to get the required sampling frequency. This is based on the formula provided in SPRUFP1 document on page 11. I'm having a hard time to find any information on the system clock frequency. I'm using the SAR Poll Example that was provided.

Please let me know my approach to set the sampling frequency is right or not?

Also, where can I find information on the system clock frequency and how do I set it up?  

Regards, 

Saba 

  • 0
    TI__Genius 12575 points

    Hi,

     

    Have you gone through section 2.1 of SAR user guide “SPRUFP1C”

     

    The SAR A/D module can operate at a maximum clock rate of 2 MHz (500 ns) and takes 32 clocks cycles to convert a value. This results in a maximum sample rate of 64 ksps. The following equations describe the relationship between the A/D programmable control registers:

     

    SAR A/D Clock Frequency = (System Clock Frequency) / (SystemClkDivisor + 1) ≤ 2 MHz

    SAR A/D Conversion Time = (SAR A/D Clock Period * 32)

     

    You can select appropriate system clock divisor based on the system clock frequency.

     

    For example if you set system clock frequency to 100MHz then choose system clock divisor such that SAR A/D clock frequency is less than or equal to 2 MHz.

     

    2MHz would result in max sampling rate of 64ksps (2MHz / 32 = 64ksps)

     

    Similarly if you need lesser sampling rate then choose appropriate divisor value to match your sampling rate.

     

    Hope this helps.

     

    Regards

    Vasanth

  • 0 in reply to Vasantha K
    Prodigy 20 points

    Hi,
    How am I supposed to set the system clock frequency?
    Do I need to change the following control registers? If so, what values should I set them to be in order to get a sampling frequency of 16KHz?

    They are currently set to these values in my code.
    param.SARCTRL = 0x3800;
    param.SARCLKCTRL = 0x000b;
    param.SARPINCTRL = 0x0100;

    and the clock divisor is set as 

    param.SysClkDiv = 0x0b; 

    Regards,
    Saba

  • 0 in reply to Saba Molani
    TI__Genius 12575 points

    Hi,

      Refer to the below link, Gel files & PLL configuration to achieve the respective frequencies are discussed here. 

     

       http://processors.wiki.ti.com/index.php/C5504/05/14/15_FAQ

      The above wiki page also has PLL calculator which you could try It out  -  C5505 PLL Calculator

      Hope this information helps.

    Regards

     Vasanth

  • 0 in reply to Saba Molani
    Prodigy 220 points
    Hey Saba,

    A suggestion that may help you is to reference the CSL_UART examples and use the getSysClk() function. From there you can just make a variable that sets the divisor based on the sampling frequency you want via simple algebra.

    Uint32 sysClk;
    Uint16 sysClkDvsor;
    sysClk = getSysClk();

    sysClkDvsor = (sysClk/(32*500))-1;

    where my desired sampling frequency in this case was 500Hz. Just an option you could look into.

    Regards,

    Ulbert