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EDMA Question

Other Parts Discussed in Thread: SYSBIOS

Hi Sir :

I work on TI AM335x platform, the tools's version are as below.

CCS V6

am335x_sysbios_ind_sdk_1.1.0.8

bios_6_41_04_54

ndk_2_24_01_18

xdctools_3_30_06_67_core

I have tested the project in starterware directory and it works fine.

However, if I add these source code in sysbios project like i2c_led, the problem below happens.

I try to add edmaTest in starterware directory in i2c_led project to test EDMA.

I add the statements after MMUInit(applMmuEntries) and I also define CH_TYPE_DMA.

/* Configure EDMA module clock */
EDMAModuleClkConfig();

/* Initialize EDMA */
EDMA3Init(EDMAAPP_EDMACC_BASE_ADDRESS, EDMAAPP_DMA_EVTQ);

_EDMAAppRegisterEdma3Interrupts();
//ConsoleUtilsPrintf("EDMAAPP_MAX_BUFFER_SIZE :%d\r\n",EDMAAPP_MAX_BUFFER_SIZE);
#ifdef CH_TYPE_DMA
EDMAAppEDMA3Test();
#else
EDMAAppQDMA3Test();
#endif

When I debug, the project always stay in the while loop below.

/* Wait for the Completion ISR. */
while(EDMAAPP_IRQ_STATUS_XFER_INPROG == IrqRaised)
{
/*
** Wait for the Completion ISR on Master Channel.
** You can insert your code here to do something
** meaningful.
*/
}

Could you give me some suggestion?

Best regards,

Marcus

  • Can you post some additional info as to exactly what you do for EDMA configuration?

    Can there be an MMU issue mapping the EDMA pages?


    Murat

  • Hi Sir:

    I appreciate your reply.

    In my platform, GPMC connects FPGA using non-multiplex and 16 bits mode.

    I can access FPGA using Synchronous single Access mode and I want to shorten 250 ns bus arbitration.

    I try use EDMA to shorten bus arbitration and I use source code below for receive.

    static unsigned int GPMCNANDRxDmaConfig(unsigned int csBaseAddr, unsigned char *data,unsigned int len)
    {
    EDMA3CCPaRAMEntry paramSet;
    /* Fill the PaRAM Set with transfer specific information */
    paramSet.aCnt = GPMC_NAND_PREFETCH_FIFO_THRLD;
    paramSet.bCnt = (len/GPMC_NAND_PREFETCH_FIFO_THRLD);
    paramSet.bCntReload = 0u;
    paramSet.cCnt = 1u;
    paramSet.destAddr = (unsigned int )(data);
    paramSet.destBIdx = GPMC_NAND_PREFETCH_FIFO_THRLD;
    paramSet.destCIdx = 1;
    paramSet.linkAddr = 0xFFFFu;
    paramSet.srcAddr = csBaseAddr;
    paramSet.srcBIdx = 0;
    paramSet.srcCIdx = 0;
    paramSet.opt = 0x00000000u;
    /* Src & Dest are in INCR modes */
    paramSet.opt &= 0xFFFFFFFCu;
    /* Setting the Transfer Complete Code(TCC). */
    paramSet.opt |= (( GPMC_EDMA_TCC_NUM << EDMA3CC_OPT_TCC_SHIFT)
    & EDMA3CC_OPT_TCC);
    /* Enabling the Completion Interrupt. */
    paramSet.opt |= (1 << EDMA3CC_OPT_TCINTEN_SHIFT);
    /* Now, write the PaRAM Set. */
    EDMA3SetPaRAM(SOC_EDMA30CC_0_REGS, GPMC_EDMA_CHANNEL_NUM, &paramSet);
    /* Now enable the transfer */
    return EDMA3EnableTransfer(SOC_EDMA30CC_0_REGS, GPMC_EDMA_CHANNEL_NUM,
    EDMA3_TRIG_MODE_EVENT);
    }

    My question is since I use the 16-bit mode for FPGA, is there something wrong with code above?

    Because the code above refer nandReadWrite.c which is in starterware directory and it uses 8-bit mode for flash.

    Another question is that does EDMA must use page/burst mode for GPMC configuration?

    Please give me some suggestions.

    Sorry for bothering you again.

    Best regards,

    Marcus
  • I've moved this thread to the device forum.

    Todd
  • Did your source code work on starterware environment?
    You said your FPGA interface is 16bit but both your configuration and destination buffer are defined for transfers of 8bit data.
    I suggestions you to read EDMA chapter in the technical manual, modify your configuration if necessary, than try in starterware because it is more simple to debug such peripherals in simple environment.
    Regards.
  • Hi Sir :

    I appreciate your reply!

    I have solved this issue.

    Best regards,

    Marcus