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6416 VCP decoding is right in simulator mode, wrong in emulator mode.

you zhou
Prodigy 30 points

I'm trying VCP on 6416. The program is running successfully in simulator mode. However, the decoding result is wrong in emulator mode if system information bits number is bigger than 63 bits, while it's all right if less than 64. I have checked the VCP control registers in the EDMA interrupt serving routing (which means the VCP decoding is over), here VCPSTAT0 register indicates that the VCP is still running. I'm confused  about this, is this the reason that the decoding result is wrong (the decoding result is always logic 0)? 

  • 0
    TI__Mastermind 35645 points

    Hi,

    Thanks for your post.

    Do you see any VCPERR bit field "ERR" bit in VCPSTAT0 being set to 1? By this, any VCPINT error interrupt is generated indicates that decode process is not engaged, do you see any error interrupt generated?

    May be, you could restart the VCP to read VCPERR and send another START command to check the status of ERR bit in VCPSTAT0 .

    Do you see VCP takes long time to process current frame? if so, you could use watchdog timer set according to the frame length and VCP configuration to allow for EDMA usage.

    Also, there are special programming consideration when you use EDMA, if the VCP EDMA transfers are not double-word aligned, it would cause errors in VCP memory. For more details on this, kindly check section 9.1.2 on the VCP user guide below:

    http://www.ti.com/lit/ug/spru533d/spru533d.pdf

    Also, I do think, there are some factors involved in how the EDMA transfers and FIFOs are set up, the alignment with memory (internal or external) for the trace-back and soft-decisions and how efficient is the ISR in servicing the VCPINT interrupt. So, kindly validate the same to succeed VCP decoding.

    Thanks & regards,

    Sivaraj K

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  • 0 in reply to Sivaraj Kuppuraj
    Prodigy 30 points
    Thanks for your reply.
    I'm sure there is no error indicated by VCPSTAT0, and hard decision memory is double aligned. Cause the hard decision is transmitted by EDMA, and I check the hard decision in EDMA ISR, so I'm sure that the EDMA has indicated that the decoding process is over.
    What I most confused is: The same project works well in simultor mode, the decoding result is all right, however, when it turns to emulator, the result is always logic zero.