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DM8148 Ipc_procSyncStart failed

Hi experts,

We are running ti8148 with rdk4.1, I've modified the DDR memory to 1G configuration, as the setting shown in bottom.

When I run load.sh to load the firmware, it hangs and continuously shows the below error. 

The shared address is weird since the ddr region is 0x80000000 to 0xC0000000, is it possible the problem cause this issue?

please give some comment, thank you very much !

Entered Ipc_procSyncStart 
remoteProcId [0x2]
sharedAddr [0xdb000000]
Entered MultiProc_self
Entered MultiProc_getNumProcessors
Entered SharedRegion_getCacheLineSize
id [0x0]
Leaving SharedRegion_getCacheLineSize
cacheLineSize [0x80]
Entered Ipc_reservedSizePerProc
Leaving Ipc_reservedSizePerProc
reservedSize [0x80]
Entered Ipc_getMasterAddr
remoteProcId [0x2]
sharedAddr [0xdb000000]
Entered MultiProc_self
Entered MultiProc_self
Leaving Ipc_getMasterAddr
master [0xdb0001a8]
Entered MultiProc_getNumProcessors
Entered SharedRegion_getCacheLineSize
id [0x0]
Leaving SharedRegion_getCacheLineSize
cacheLineSize [0x80]
Entered Ipc_reservedSizePerProc
Leaving Ipc_reservedSizePerProc
reservedSize [0x80]
Entered Ipc_getSlaveAddr
remoteProcId [0x2]
sharedAddr [0xdb000000]
Entered MultiProc_self
Entered MultiProc_self
Leaving Ipc_getSlaveAddr
slave [0xdb000128]
Entered MultiProc_self
Leaving Ipc_procSyncStart 
status [0xfffffff5]
Ipc_attach: Ipc_procSyncStart failed!

//Memory configuration

/*-------------------------------------------------------- 1ST 512MB */
var DDR3_ADDR_REG0_START = 0x80000000;
var DDR3_ADDR_REG0_END = 0xA0000000;
/*-------------------------------------------------------- 2ND 512MB */
var DDR3_ADDR_REG1_START = 0xA0000000;
var DDR3_ADDR_REG1_END = 0xC0000000;


var OCMC0_ADDR = 0x40300000;
/*OCMC1 exisits only for TI816X*/
var OCMC1_ADDR = 0x40400000;

var OCMC_SIZE = 128*KB;

var OCMC0_VIDEO_M3_SIZE = 16*KB;
var OCMC0_VPSS_M3_SIZE = OCMC_SIZE - OCMC0_VIDEO_M3_SIZE;

var OCMC0_VIDEO_M3_ADDR = OCMC0_ADDR;
var OCMC0_VPSS_M3_ADDR = OCMC0_VIDEO_M3_ADDR + OCMC0_VIDEO_M3_SIZE;

var OCMC0_RUN_ADDR = 0x00300000;
var OCMC0_VIDEO_M3_RUN = OCMC0_RUN_ADDR;
var OCMC0_VPSS_M3_RUN = OCMC0_VIDEO_M3_RUN + OCMC0_VIDEO_M3_SIZE;

var M3_L2_RAM = 0x55024000;
var M3_L2_RAM_SIZE = 48*KB;

var M3_L2_RAM_MAPPED = 0x20004000;

var TOTAL_MEM_SIZE = 1024*MB;


/* first 512MB */
var LINUX_SIZE = 383*MB;
var SR1_SIZE = 64*MB;
var VIDEO_M3_CODE_SIZE = 5*MB
var VIDEO_M3_DATA_SIZE = 6*MB;
var VIDEO_M3_BSS_SIZE = 15*MB;
var DSS_M3_CODE_SIZE = 1*MB;
var DSS_M3_DATA_SIZE = 5*MB;
var DSS_M3_BSS_SIZE = 15*MB;
var DSP_CODE_SIZE = 2*MB;
var DSP_DATA_SIZE = 15*MB;
var TILER_SIZE = 256*MB-128*MB-127*MB; /* Reducing this to fix Vid Frame Alloc failures. Need to fix */ /* MUST be aligned on 128MB boundary */

/* second 512MB */
var SR2_FRAME_BUFFER_SIZE = 499*MB;
var SR0_SIZE = 4*MB - 256*KB + 2*MB;
var VIDEO_M3_EXCEPTION_CTX_SIZE = 128*KB;
var VPSS_M3_EXCEPTION_CTX_SIZE = 128*KB;
var HDVPSS_DESC_SIZE = 2*MB;
var HDVPSS_SHARED_SIZE = 2*MB;
var NOTIFY_SHARED_SIZE = 2*MB;
var REMOTE_DEBUG_SIZE = 1*MB;


var LINUX_ADDR = DDR3_ADDR_REG0_START;
var SR1_ADDR = LINUX_ADDR + LINUX_SIZE;
var VIDEO_M3_CODE_ADDR = SR1_ADDR + SR1_SIZE;
var VIDEO_M3_DATA_ADDR = VIDEO_M3_CODE_ADDR + VIDEO_M3_CODE_SIZE;
var VIDEO_M3_BSS_ADDR = VIDEO_M3_DATA_ADDR + VIDEO_M3_DATA_SIZE;

var VIDEO_M3_BSS_ADDR_RUN = VIDEO_M3_BSS_ADDR - DDR3_ADDR + 0x20000000;

var DSS_M3_CODE_ADDR = VIDEO_M3_BSS_ADDR + VIDEO_M3_BSS_SIZE;
var DSS_M3_DATA_ADDR = DSS_M3_CODE_ADDR + DSS_M3_CODE_SIZE;
var DSS_M3_BSS_ADDR = DSS_M3_DATA_ADDR + DSS_M3_DATA_SIZE;
var DSS_M3_BSS_RUN = DSS_M3_BSS_ADDR - DDR3_ADDR + 0x20000000;
var DSP_CODE_ADDR = DSS_M3_BSS_ADDR + DSS_M3_BSS_SIZE;
var DSP_DATA_ADDR = DSP_CODE_ADDR + DSP_CODE_SIZE;
var TILER_ADDR = DSP_DATA_ADDR + DSP_DATA_SIZE;

var SR2_FRAME_BUFFER_ADDR = DDR3_ADDR_REG1_START;
var SR0_ADDR = SR2_FRAME_BUFFER_ADDR + SR2_FRAME_BUFFER_SIZE;
var VIDEO_M3_EXCEPTION_CTX_ADDR = SR0_ADDR + SR0_SIZE;
var VPSS_M3_EXCEPTION_CTX_ADDR = VIDEO_M3_EXCEPTION_CTX_ADDR + VIDEO_M3_EXCEPTION_CTX_SIZE;

var HDVPSS_DESC_ADDR = VPSS_M3_EXCEPTION_CTX_ADDR + VPSS_M3_EXCEPTION_CTX_SIZE;
var HDVPSS_SHARED_ADDR = HDVPSS_DESC_ADDR + HDVPSS_DESC_SIZE;
var NOTIFY_SHARED_ADDR = HDVPSS_SHARED_ADDR + HDVPSS_SHARED_SIZE;
var REMOTE_DEBUG_ADDR = NOTIFY_SHARED_ADDR + NOTIFY_SHARED_SIZE;

Best Regards, 

Dwayne

  • Hi Dwayne,

    Dwayne Johnson said:
    We are running ti8148 with rdk4.1, I've modified the DDR memory to 1G configuration

    I am not familiar with DVR RDK, but I think that the default configuration should be for 1GB DDR RAM, thus no need to modify. If not 1GB, what is the default configuration?

    Please provide me also the values you have in the below registers:

    DMM_LISA_MAP_0
    DMM_LISA_MAP_1
    DMM_LISA_MAP_2
    DMM_LISA_MAP_3

    Regards,
    Pavel

  • Hi Pavel,

    Thanks for reply !
    Here is the values:

    /*
    * TI814X PG2.1 DMM LISA MAPPING
    * 1G contiguous section with 128-byte interleaving
    */
    #define PG2_1_DMM_LISA_MAP__0 0x0
    #define PG2_1_DMM_LISA_MAP__1 0x0
    #define PG2_1_DMM_LISA_MAP__2 0x0
    #define PG2_1_DMM_LISA_MAP__3 0x80640300




    Default DDR size sets to 1G, but only 512MB is used, it is also confused me.
    var DDR3_ADDR = 0x80000000;
    var DDR3_SIZE = 1 * GB;
    var DDR3_ADDR_REG0_START = 0x80000000;
    var DDR3_ADDR_REG0_END = 0x90000000;
    var DDR3_ADDR_REG1_START = 0xB0000000;
    var DDR3_ADDR_REG1_END = 0xC0000000;


    Best Regards,
    Dwayne

  • Dwayne,

    Dwayne Johnson said:
    /*
    * TI814X PG2.1 DMM LISA MAPPING
    * 1G contiguous section with 128-byte interleaving
    */
    #define PG2_1_DMM_LISA_MAP__0 0x0
    #define PG2_1_DMM_LISA_MAP__1 0x0
    #define PG2_1_DMM_LISA_MAP__2 0x0
    #define PG2_1_DMM_LISA_MAP__3 0x80640300

    These value you get from u-boot or linux kernel? Are you using DM814x TI EVM/DVR board or custom board?

    Let we start with u-boot. The default setup is for 512MByte DDR3 RAM. You will need to comment the below lines of code to switch to 1GByte DDR3:

    u-boot-dvr-rdk-dm81xx/include/asm/arch-ti81xx/ddr_defs_ti814x.h

    //#define DDR_MEM_512M    // For McFW default configuration of 512 MB

    u-boot-dvr-rdk-dm81xx/board/ti/ti8148/evm.c

    //#define DDR_MEM_512M    /* Making 512MB as default config in DVR RDK for 8148 */

    u-boot-dvr-rdk-dm81xx/include/configs/ti8148_evm.h

    /**
     * Physical Memory Map
     */

     #define CONFIG_NR_DRAM_BANKS           2               /* we have 2 banks of DRAM */
     #define PHYS_DRAM_1                    0x80000000      /* DRAM Bank #1 */
    //#define PHYS_DRAM_1_SIZE               0x40000000      /* 1 GB */
    //#define PHYS_DRAM_2                    0xC0000000      /* DRAM Bank #2 */
    //#define PHYS_DRAM_2_SIZE               0x40000000      /* 1 GB */
    #define PHYS_DRAM_1_SIZE               0x20000000      /* 512 MB */
    #define PHYS_DRAM_2                    0xA0000000      /* DRAM Bank #2 */
    #define PHYS_DRAM_2_SIZE               0x20000000      /* 512 MB */

    See also the below e2e threads for how to config 1GB RAM:

    Regards,
    Pavel

  • Hi Pavel, 

    Sorry for lately reply, really thanks for your reply!

    We are using custom board with 4*256MB DDR.

    I tried the suggestion you mentioned above, but the timeout problem is still occurred during the ipc_attach().

    I've  check threads discussed about ram configuration,

    but looks dvrrdk4.1 has some new variables such as DSS_M3_BSS_SIZE, the configuration table is different. 

    Is there any configuration wrong in my setting?

    // ipc_attach timeout log

    Entered Ipc_attach 
    remoteProcId [0x2]
    Entered SharedRegion_getEntry
    id [0x0]
    entry [0xd52f5df4]
    Entered Memory_copy
    dst [0xd52f5df4]
    src [0xd84de000]
    len [0x1c]
    Leaving MemoryOS_copy
    dst [0xd52f5df4]
    Leaving SharedRegion_getEntry
    status [0x0]
    Entered MultiProc_self
    Entered MultiProc_self
    Entered MultiProc_getNumProcessors
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered Ipc_reservedSizePerProc
    Leaving Ipc_reservedSizePerProc
    reservedSize [0x80]
    Entered Ipc_getSlaveAddr
    remoteProcId [0x2]
    sharedAddr [0xdb000000]
    Entered MultiProc_self
    Entered MultiProc_self
    Leaving Ipc_getSlaveAddr
    slave [0xdb000128]
    Entered MultiProc_getNumProcessors
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered Ipc_reservedSizePerProc
    Leaving Ipc_reservedSizePerProc
    reservedSize [0x80]
    Entered SharedRegion_isCacheEnabled
    id [0x0]
    Leaving SharedRegion_isCacheEnabled
    cacheEnable [0x0]
    Entered Ipc_procSyncStart 
    remoteProcId [0x2]
    sharedAddr [0xdb000000]
    Entered MultiProc_self
    Entered MultiProc_getNumProcessors
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered Ipc_reservedSizePerProc
    Leaving Ipc_reservedSizePerProc
    reservedSize [0x80]
    Entered Ipc_getMasterAddr
    remoteProcId [0x2]
    sharedAddr [0xdb000000]
    Entered MultiProc_self
    Entered MultiProc_self
    Leaving Ipc_getMasterAddr
    master [0xdb0001a8]
    Entered MultiProc_getNumProcessors
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered Ipc_reservedSizePerProc
    Leaving Ipc_reservedSizePerProc
    reservedSize [0x80]
    Entered Ipc_getSlaveAddr
    remoteProcId [0x2]
    sharedAddr [0xdb000000]
    Entered MultiProc_self
    Entered MultiProc_self
    Leaving Ipc_getSlaveAddr
    slave [0xdb000128]
    Entered MultiProc_self
    Leaving Ipc_procSyncStart 
    status [0xfffffff5]
    Ipc_attach: Ipc_procSyncStart failed! 
    Entered Notify_intLineRegistered
    procId [0x2]
    lineId [0x0]
    Leaving Notify_intLineRegistered
    isRegistered [0x1]
    Entered NameServerRemoteNotify_sharedMemReq
    params [0x0]
    Entered MultiProc_getNumProcessors
    Leaving NameServerRemoteNotify_sharedMemReq
    totalSize [0x300]
    Entered MultiProc_self
    Entered SharedRegion_getPtr
    srPtr [0x0]
    Leaving SharedRegion_getPtr
    returnPtr [0xdb000000]
    Entered TransportShmSetup_sharedMemReq
    sharedAddr [0xdb000000]
    Entered MultiProc_getNumProcessors
    Entered TransportShm_Params_init
    params [0xd52f5dbc]
    Entered Memory_copy
    dst [0xd52f5dbc]
    src [0xbf084188]
    len [0xc]
    Leaving MemoryOS_copy
    dst [0xd52f5dbc]
    Leaving TransportShm_Params_init
    Entered TransportShm_sharedMemReq
    params [0xd52f5dbc]
    Entered SharedRegion_getId
    addr [0xdb000000]
    Entered GateMutex_enter
    gmHandle [0xd84e4000]
    Entered OsalMutex_enter
    mutexHandle [0xd84e7000]
    btsm_out_thread_func 462
    Leaving OsalMutex_enter
    Leaving GateMutex_enter
    key [0x0]
    Entered GateMutex_leave
    gmHandle [0xd84e4000]
    Entered OsalMutex_leave
    mutexHandle [0xd84e7000]
    key [0x0]
    Leaving OsalMutex_leave
    Leaving GateMutex_leave
    Leaving SharedRegion_getId
    regionId [0x0]
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered ListMP_Params_init
    params [0xd52f5d88]
    Entered Memory_copy
    dst [0xd52f5d88]
    src [0xbf083cec]
    len [0x10]
    Leaving MemoryOS_copy
    dst [0xd52f5d88]
    Leaving ListMP_Params_init
    Entered ListMP_sharedMemReq
    params [0xd52f5d88]
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Leaving ListMP_sharedMemReq
    memReq [0x80]
    Entered ListMP_sharedMemReq
    params [0xd52f5d88]
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Entered SharedRegion_getCacheLineSize
    id [0x0]
    Leaving SharedRegion_getCacheLineSize
    cacheLineSize [0x80]
    Leaving ListMP_sharedMemReq
    memReq [0x80]
    Leaving TransportShm_sharedMemReq
    memReq [0x200]
    Leaving TransportShmSetup_sharedMemReq
    memReq [0x200]
    Entered MultiProc_self
    Entered SharedRegion_getPtr
    srPtr [0x0]
    Leaving SharedRegion_getPtr
    returnPtr [0xdb000000]
    Leaving Ipc_attach

    Sincerely,

    Dwayne

  • Hi Pavel,

    Sorry for lately reply, many thanks for your response!
    I'm using a custom board with 4*256MB DDR.
    I followed your comment to make the modification in uboot, but timeout problem is still existed during the ipc_attach();
    I've refer the threads discussed about the ddr configuration, but dvrrdk4.1 has some new variables different than previous version.
    Is there any wrong configuration in my setting?

    Thank you again,
    Dwayne
  • Dwayne,

    ipc_attach() code is based on linux kernel, not on u-boot code. Can you apply these u-boot DDR settings to the linux kernel?

    As you are using custom board, this might be also HW or timing issue. Have you made DDR3 SW leveling? Do you test the DDR3 HW with the u-boot mtest?

    Regards,
    Pavel
  • Hi Pavel,

    Big thanks for your replay.
    Sorry for insufficient information,
    I'm working on firmware upgrading from rdk3.5 to rdk4.1.
    Since everything could work fine when using rdk3.5, it may not be HW problem.
    The timeout problem during ipc_attach() occurred when I replaced the firmware by newer ones.
    I check all the similar problems in forum, but have not found any information about changing the DDR setting in kernel. Could you give a guidance about it?

    Many thanks,
    Dwayne
  • Dwayne,

    Dwayne Johnson said:
    I'm working on firmware upgrading from rdk3.5 to rdk4.1.

    You upgrade the whole RDK from rdk3.5 to rdk4.1, or you upgrade only some specific firmware from the version found in rdk3.5 to the new version found in rdk4.1?

    Dwayne Johnson said:
    Since everything could work fine when using rdk3.5, it may not be HW problem.
    The timeout problem during ipc_attach() occurred when I replaced the firmware by newer ones.

    Do you call rdk3.5 and rdk4.1 a firmware?

    Dwayne Johnson said:
    I check all the similar problems in forum, but have not found any information about changing the DDR setting in kernel. Could you give a guidance about it?

    Please provide me the values you have in the below registers, get the values from user space (i.e. with devmem2 tool).

    DMM_LISA_MAP_0
    DMM_LISA_MAP_1
    DMM_LISA_MAP_2
    DMM_LISA_MAP_3

    BR
    Pavel

  • Hi Pavel,

    You upgrade the whole RDK from rdk3.5 to rdk4.1, or you upgrade only some specific firmware from the version found in rdk3.5 to the new version found in rdk4.1?
    >> yes, i changed dsp, m3 video and vpss firmwares.

    Do you call rdk3.5 and rdk4.1 a firmware?
    >> sorry for my expression, i mean this problem happened after i changed to upgraded firmwares.

    Please provide me the values you have in the below registers, get the values from user space (i.e. with devmem2 tool).
    >>
    /ti814x/bin # ./devmem2.o 0x80640300
    /dev/mem opened.
    Memory mapped at address 0x4028d000.
    Value at address 0x80640300 (0x4028d300): 0x0

    I also try the following test:

    /ti814x/bin # ./mem_rdwr.out --rd a0003000

    0xa0003000: 00000000

    /ti814x/bin # ./mem_rdwr.out --wr a0003000 123

    ORG 0xa0003000: 0
    NEW 0xa0003000: 123

    /ti814x/bin # ./mem_rdwr.out --rd a0003000

    0xa0003000: 00000123

    /ti814x/bin # ./mem_rdwr.out --rd 80003000

    0x80003000: FFFFFFFF

    /ti814x/bin # ./mem_rdwr.out --wr 80003000 123

    ORG 0x80003000: ffffffff
    NEW 0x80003000: 123

    /ti814x/bin # ./mem_rdwr.out --rd 80003000

    0x80003000: 00000123

    /ti814x/bin # ./mem_rdwr.out --rd a0003000

    0xa0003000: 00000123

    /ti814x/bin # ./mem_rdwr.out --wr a0003000 123

    ORG 0xa0003000: 123
    NEW 0xa0003000: 123

    /ti814x/bin # ./mem_rdwr.out --rd a0003000

    0xa0003000: 00000123

    /ti814x/bin # ./mem_rdwr.out --rd b0003000

    0xb0003000: FFFFFFFF

    /ti814x/bin # ./mem_rdwr.out --wr b0003000 123

    ORG 0xb0003000: ffffffff
    NEW 0xb0003000: 123

    /ti814x/bin # ./mem_rdwr.out --rd b0003000

    0xb0003000: 00000123
  • Dwayne Johnson said:
    You upgrade the whole RDK from rdk3.5 to rdk4.1, or you upgrade only some specific firmware from the version found in rdk3.5 to the new version found in rdk4.1?
    >> yes, i changed dsp, m3 video and vpss firmwares.

    Yes you upgrade the whole RDK or yes you upgrade only specific firmware?

    Dwayne Johnson said:
    Do you call rdk3.5 and rdk4.1 a firmware?
    >> sorry for my expression, i mean this problem happened after i changed to upgraded firmwares.

    Do you use rdk3.5 with firmware (dsp,m3 video and vpss) from rdk4.1?

    Dwayne Johnson said:
    Please provide me the values you have in the below registers, get the values from user space (i.e. with devmem2 tool).
    >>
    /ti814x/bin # ./devmem2.o 0x80640300
    /dev/mem opened.
    Memory mapped at address 0x4028d000.
    Value at address 0x80640300 (0x4028d300): 0x0

    This is not what I asked for. Please provide me the values of the below registers with devmem2 tool:

    DMM_LISA_MAP_0/0x4E000040
    DMM_LISA_MAP_1/0x4E000044
    DMM_LISA_MAP_2/0x4E000048
    DMM_LISA_MAP_3/0x4E00004C


    Regards,
    Pavel

  • Hi Pavel,

    Thanks for your reply,

    I found that when i comment out:
    .text_ipc_bios {
    -lipc.lib(.text)
    // -lsysbios.lib(.text)
    } load >> OCMC0_VPSS_M3_RAM, run >> OCMC0_VPSS_M3_RAM_MAPPED

    Ipc_procSyncStart failed problem is solved, but another problem happened:

    [m3vpss ] 4871: SYSTEM: All VPDMA Free !!!
    [m3vpss ] === I2C0/2 Clk is active ===
    [m3vpss ] 4889: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_0] in region 0 ...
    [m3vpss ] 4890: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_0] in region 0 ...
    [m3vpss ] 4890: SYSTEM: ListElem Shared Addr = 0xa03d6200
    [m3vpss ] 4892: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_1] in region 0 ...
    [m3vpss ] 4892: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_1] in region 0 ...
    [m3vpss ] 4892: SYSTEM: ListElem Shared Addr = 0xa03d9700
    [m3vpss ] 4904: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_22] in region 0 ...
    [m3vpss ] 4904: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_22] in region 0 ...
    [m3vpss ] 4904: SYSTEM: ListElem Shared Addr = 0xa03dcc00
    [m3vpss ] 4907: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_23] in region 0 ...
    [m3vpss ] 4907: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_23] in region 0 ...
    [m3vpss ] 4907: SYSTEM: ListElem Shared Addr = 0xa0402400
    [m3vpss ] 4910: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_24] in region 0 ...
    [m3vpss ] 4910: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_24] in region 0 ...
    [m3vpss ] 4910: SYSTEM: ListElem Shared Addr = 0xa0427c00
    [m3vpss ] 4916: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_27] in region 0 ...
    [m3vpss ] 4917: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_27] in region 0 ...
    [m3vpss ] 4917: SYSTEM: ListElem Shared Addr = 0xa044d400
    [m3vpss ] 4919: SYSTEM: Creating ListMP [VPSS-M3_IPC_OUT_28] in region 0 ...
    [m3vpss ] 4919: SYSTEM: Creating ListMP [VPSS-M3_IPC_IN_28] in region 0 ...
    [m3vpss ] 4920: SYSTEM: ListElem Shared Addr = 0xa046be80
    [m3vpss ] 4921: SYSTEM : HDVPSS Drivers Version: HDVPSS_01_00_01_37
    [m3vpss ] 4921: SYSTEM : FVID2 Init in progress !!!
    [m3vpss ] Unhandled Exception:
    [m3vpss ] Exception occurred in ThreadType_Task
    [m3vpss ] handle: 0x3e488658.
    [m3vpss ] stack base: 0x3ed40a80.
    [m3vpss ] stack size: 0x8000.
    [m3vpss ] R0 = 0x3ed959b4 R8 = 0xffffffff
    [m3vpss ] R1 = 0x00000001 R9 = 0xffffffff
    [m3vpss ] R2 = 0x3ed959b8 R10 = 0xffffffff
    [m3vpss ] R3 = 0x3ed4890c R11 = 0xffffffff
    [m3vpss ] R4 = 0x3ed959b0 R12 = 0x0030897d
    [m3vpss ] R5 = 0x00000000 SP(R13) = 0x3ed489a8
    [m3vpss ] R6 = 0x00000001 LR(R14) = 0x9d5d06b7
    [m3vpss ] R7 = 0xffffffff PC(R15) = 0x0030897c
    [m3vpss ] PSR = 0x01000000
    [m3vpss ] ICSR = 0x0440f803
    [m3vpss ] MMFSR = 0x00
    [m3vpss ] BFSR = 0x01
    [m3vpss ] UFSR = 0x0000
    [m3vpss ] HFSR = 0x40000000
    [m3vpss ] DFSR = 0x00000000
    [m3vpss ] MMAR = 0xe000ed34
    [m3vpss ] BFAR = 0xe000ed38
    [m3vpss ] AFSR = 0x00000000
    [m3vpss ] Terminating Execution...


    and if i comment out the whole link cmd file link_hdvpss.cmd in DVRRDK_04.01.00.02/dvr_rdk/makerules/rules_m3.mk,
    ifeq ($(SOC),ti814x)
    #MISC_LNKCMD_INCLUDE = $(dvr_rdk_PATH)/mcfw/src_bios6/cfg/ti814x/link_hdvpss.cmd
    MISC_LNKCMD_INCLUDE =
    endif

    Firmware could be loaded correctly, do you have any ideas?

  • Dwayne,

    This looks to be DVRRDK specific, and I am not aware with DVRRDK. You should contact your local TI FAE regarding DVRRDK specific questions.

    Regards,
    Pavel