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About DM8168 PCIe problem

user4489731
Intellectual 890 points

Hi,

   I use AMC-PCIe adapter card  to connect DM8168 EVM and C6678 EVM board,DM8168 work as RC and C6678 as EP.I met some problem as following:

  1.After link training success，I have checked some PCIe registers，the value is：

    PL_LINK_CTRL:0x30120（both DM8168 and C6678）

   PL_GEN2:0x20F(both DM8168 and C6678)

   LINK_CAP:0x135422（DM8168），0x35422(C6678)

  LINK_STAT_CTRL:0x30120008(DM8168),0x10120080(C6678)

  SERDES_CFG0:0x622A0(DM8168), 0x62320(C6678)

  SERDES_CFG1:0x222A0(DM8168).0x22320(C6678)

 According to LINK_STAT_CTRL register，we can see NEGOTIATED_LINK_WD is 0x1,only use x1 lane.both DM8168 and C6678 support x2 lane.what can I do to change x1 mode to x2？

2. To solve problem1, I checked the value of PCIE_SERDES_STS register in C6678，the value is 0x00000201，according to document: "Loss of Signal detect of Lane1. Driven high asynchronously when a loss of signal (electrical idle) condition is detected."so I think the problem occured on lane1，why loss of signal detect of lane1？How can I solve it？

Best wishes,

Simon

  • 0
    TI__Guru**** 170625 points

    user4489731 said:
     According to LINK_STAT_CTRL register，we can see NEGOTIATED_LINK_WD is 0x1,only use x1 lane.both DM8168 and C6678 support x2 lane.what can I do to change x1 mode to x2？

    I can comment from the DM816x side. DM816x devices are x2 link devices (2 lanes) and when connected to a peer with link capability of x2 and onwards (e.g., x2, x4, x8 or x16) will negotiate to x2.

    user4489731 said:
    LINK_CAP:0x135422（DM8168）

    user4489731 said:
    PL_LINK_CTRL:0x30120（both DM8168

    From these registers I can say DM816x is in x2 mode already.

    LINK_CAP[9:4] MAX_LINK_WIDTH = 0x2 (x2 mode)

    PL_LINK_CTRL[21:16] LNK_MODE = 0x3 (x2 mode)

    I can provide you the below pointers for more info regarding DM816x PCIe RC driver:

    user4489731 said:
    2. To solve problem1, I checked the value of PCIE_SERDES_STS register in C6678，the value is 0x00000201，according to document: "Loss of Signal detect of Lane1. Driven high asynchronously when a loss of signal (electrical idle) condition is detected."so I think the problem occured on lane1，why loss of signal detect of lane1？How can I solve it？

    This question looks to be specific for C6678 device, and I will recommend you to post/ask in C6678 forum. And I see you are already post there:

    Regards,
    Pavel

  • 0 in reply to Pavel Botev
    Intellectual 890 points

    Hi,Pavel,

        Thank you for your answer.

        In DM8168,will there be the factor about SW may cause this problem?such as，if turn off some switches，it is only can enable one lane？ 

        Best wishes，

        Simon

  • 0 in reply to user4489731
    TI__Guru**** 170625 points
    Simon,

    If you attach x1 PCIe EP on the other side of the DM816x PCIe RC, they will negotiate to x1 (as DM816x PCIe support both x1 and x2).

    If you attach x2 PCIe EP (or x4, x8, x16) on the other side of the DM816x PCIe RC, they will negotiate to x2. If you want to force x1 operation in this case, then this can be achieved by setting following bits in corresponding registers before enabling link training (LTSSM).

    LINK_CAP[9:4] = 1 i.e., MAX_LINK_WIDTH = 1 @0x5100107c
    PL_LINK_CTRL[21:16] = 1 i.e., LNK_MODE = 1 @0x51001710

    Note that alternatively you may be able to force x1 link from the peer, if it has support for such configuration.

    Also, this configuration can be set even after link is already established in x2 mode. In such case, the link needs to be disabled before setting above configuration and then enable and trigger link training.

    BR
    Pavel