I'm using the c6657 dev board. spra947a.pdf has an example for N=1024:
/* stage one */
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I'm using the c6657 dev board. spra947a.pdf has an example for N=1024:
/* stage one */
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None of those threads deal with multi pass.
As I said, I have implemented DSPF_sp_fftSPxSP() and it works for the single pass case with 1024 bins. It fails with an incorrect result when tried with the multi pass use described in TI documentation. Is there a documentaion error? Am I calling it correctly? I did copy the SPRU's example directly for 1024 yet it produces incorrect results.
Rob, here is what I suggest, if you already did it we will continue
1. Run the simple 256 complex FFT example from the release and make sure that it works for you. Look at directory dsplib_c66x_3_4_0_0\examples\fft_sp_ex of the release
2. Do search on FFT decimation in frequency. This will give you the basic understanding of how the multi-path is working. The first pass uses the global twiddle factors (generated with the "real" N) but the number of passes is not log(N) (or half of it when Radix 4 is used) but rather until the blocks are of 256 complex elements. The Web is full of materials about Decimation in Frequency.
Again, understand decimation in frequency and how it works
Best regards
Ran