AM335x cpufreq warnings

Hi,

I have a AM335x board with customised kernel image and DTB.  Everything worked so far and I am trying to clean up as much as I can all the 'user.warn' and 'user.err' kernel messages but I have a few below that after searching the forum, googling, etc... I couldn't get rid of... Please could someone kindly help please? I think they all related to the clocking but I am not entirely sure.

(1)

Mar 27 22:14:12 localhost user.warn kernel: cpufreq_cpu0: failed to get cpu0 regulator: -19
Mar 27 22:14:12 localhost user.err kernel: cpufreq_cpu0: Bootloader freq 550000000Hz no match to table, Using 300000000Hz

(2)

Mar 27 22:14:12 localhost user.err kernel: platform mpu.1: FIXME: clock-name 'fck' DOES NOT exist in dt!

Mar 27 22:14:12 localhost user.err kernel: platform 49000000.edma: FIXME: clock-name 'fck' DOES NOT exist in dt!

Mar 27 22:14:12 localhost user.err kernel: platform 56000000.sgx: FIXME: clock-name 'fck' DOES NOT exist in dt!

I did see someone has asked (2) before https://e2e.ti.com/support/arm/sitara_arm/f/791/t/388498

but I still don't know how to fix them... below is the section of clocks mentioned are supposed to be relevant in my DTB:

cpus {
                #address-cells = <0x1>;
                #size-cells = <0x0>;

                cpu@0 {
                        compatible = "arm,cortex-a8";
                        device_type = "cpu";
                        reg = <0x0>;
                        operating-points = <0xf4240 0x149d58 0xc3500 0x139b88 0xafc80 0x139b88 0x927c0 0x12b128 0x7a120 0x112a88 0x493e0 0x112a88 0x43238 0x112a88>;
                        voltage-tolerance = <0x2>;
                        platform-opp-modifier = <0x2>;
                        clocks = <0x3>;
                        clock-names = "cpu";
                        clock-latency = <0x493e0>;
                        cpu0-supply = <0x4>;
                };
        };

dpll_mpu_m2_ck@44e004a8 {
                        #clock-cells = <0x0>;
                        compatible = "ti,divider-clock";
                        clocks = <0x3>;
                        reg = <0x44e004a8 0x4>;
                        bit-mask = <0x1f>;
                        index-starts-at-one;
                };
l3_gclk {
                        #clock-cells = <0x0>;
                        compatible = "fixed-factor-clock";
                        clocks = <0x5d>;
                        clock-mult = <0x1>;
                        clock-div = <0x1>;
                        linux,phandle = <0x9>;
                        phandle = <0x9>;
                };

gfx_fck_div_ck@44e0052c {
                        #clock-cells = <0x0>;
                        compatible = "ti,divider-clock";
                        clocks = <0x63>;
                        reg = <0x44e0052c 0x4>;
                        table = <0x1 0x0 0x2 0x1>;
                        bit-mask = <0x1>;
                };

Many thanks in advanced.