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Max SPIx_CLK slave mode frequency for OMAP

Other Parts Discussed in Thread: OMAPL138

When an SPI in the OMAPL138 is configured for a slave what is the maximum frequency permitted on the SPIx_CLK input?  Does it have the same maximum as for master mode or can it go as fast as the SPI module clock?

 

I'm finding somewhat contradictory information related to this signal in the documentation

TMS320C674x/OMAP-L1x Processor Serial Peripheral Interface (SPI) User's Guide
Literature Number: SPRUFM4G January 2010
http://focus.ti.com/lit/ug/sprufm4g/sprufm4g.pdf

I suspect the following sections contain typos.

1.2 Features
The SPI allows software to program the following options:
SPIx_CLK frequency (SPI module clock/2 through SPI module clock/256)

The rest of the guide consistently indicates a maximum of 1/3 the module clock.

2.6 Slave Mode Settings
Note that in certain cases the allowed values may still be ignored.
Table 6. Allowed SPI Register Settings in Slave Modes
SPIFMTn (1) PRESCALE 2 to FFh

PRESCALE doesn't make sense when in slave mode since the SPIx_CLK is asynchronous to the SPI module clock.

 

I think the following section best describes the SPI clock.  Note that the PRESCALE value after reset is 0.

3.18 SPI Data Format Registers (SPIFMTn)
Table 26. SPI Data Format Register (SPIFMTn) Field Descriptions
SPI prescaler. It determines the bit transfer rate if the SPI is the network master and is directly derived from the SPI module clock.  If the SPI is configured as slave, PRESCALE does not need to be configured.  The clock rate can be calculated as: SPI clock frequency = SPI module clock/(PRESCALE + 1)  Note: PRESCALE values less than 2h are not supported.

 

  • In Table 6-62 of the datasheet, it gives the min and max cycle times for SPI0_CLK, for each operating point, when operating as a slave.

    Jeff

  • The datasheet indicates the absolute maximum SPIx_CLK frequencies for each core voltage. I hadn't considered these before, but I will now, thanks.

    However this information contradicts information in the SPI User's Guide.

    Table 6-61. General Timing Requirements for SPI0 Master Modes(1)
    tc(SPC)M Cycle Time, SPI0_CLK, All Master Modes min 20/30/40ns(2) max 256P
    Table 6-62. General Timing Requirements for SPI0 Slave Modes(1)
    tc(SPC)S Cycle Time, SPI0_CLK, All Slave Modes min 40/50/60ns(2) max 256P
    (1) P = SYSCLK2 period;
    (2) This timing is limited by the timing shown or 2P, whichever is greater.

    It agrees with the information in section 1.2 Features of the SPI User's Guide, but disagrees with the information in sections 2.5 Master Mode Settings and 3.18 SPI Data Format Registers (SPIFMTn). Can I please get confirmation of which documentation is incorrect? Is minimum PRESCALE setting 1 or 2 (resulting in a minimum divide of 2 or 3)?

    Can I also get confirmation of which section of 2.6 Slave Mode Settings or section 3.18 SPI Data Format Registers (SPIFMTn) is incorrect with respect to PRESCALE setting in slave mode? Does PRESCALE need to be configured in slave mode?

  • If the device is running at 300MHz, SYSCLK2 = 150MHz, which is the SPI module clock.

    According to the datasheet table 6-61, the maximum frequency is 1/20ns = 50 MHz.

    Setting PRESCALE = 2 means SPI_CLK = 150MHz / (2+1) = 50MHz.

    Section 2.6 states: "Note that in certain cases the allowed values may still be ignored." According to the note in Table 26: "If the SPI is configured as slave, PRESCALE does not need to be configured." So PRESCALE is one of the allowed values that may be ignored in Table 6.

    Jeff

  • Sorry, let me restate my questions as follows

    If the device is running at 100 MHz, SYSCLK2 = 50 MHz.  According to the datasheet table 6-61, the maximum frequency would be 1/(2P) = 25 MHz which would require setting PRESCALE to 1 which is an invalid value according to the user guide.  Should the minimum clock period be 3P or should PRESCALE = 1 be valid?

    Section 3.18 indicates PRESCALE does not need to be configured, implying its reset value of 0 may be preserved.  However section 2.6 indicates that only 2 to FFh are the allowed values, implying that 0 and 1 are not allowed. i.e. it must contain an allowed value even though it will be ignored.  Does PRESCALE need to be configured to a valid value or are 0 to FFh valid values in slave mode?

  • 1) In this case you are correct, the minimum clock period should be 3P. I checked with the datasheet owner and he said that it has already been corrected in the next revision.

    2) Even though the value is ignored, it is good practice to follow the requirements of the documentation, so I would recommend to go ahead and program 2 into the PRESCALE register.

    Jeff

  • Thank-you Jeff for your confirmations.  I assume the same minimum clock period of 3P applies to both master and slave modes.

    So in conclusion these are the manual sections that are incorrect and which will be updated in next revisions

    The notes for Table 6-61 & Table 6-62 will indicate This timing is limited by the timing shown or 3P, whichever is greater

    1.2 Features will indicate SPI module clock/3 is the maximum SPIx_CLK frequency.

    3.18 SPI Data Format Registers (SPIFMTn) will indicate that if the SPI is configured as slave, PRESCALE will be ignored but does need to be configured to a valid value.