Hi,
The question I early posted here:https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/500671
The value of PCIE_SERDES_STS is 0x201,so the issue is "loss of signal on lane1",The SW I set in C6678 as following:
SW6[4:1]=0000,SW5[4:1]=0000,SW4[4:1]=0000,SW3[4:1]=0001
How can I solve the problem?
Best wishes,
Simon
