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C5535 ezDSP SAR Sampling Frequency/Clock Divider issue

Ulbert Botero
Prodigy 220 points

Hey,

I'm working on using the SAR ADC on the C5535 ezDSP and have run into the issue where I can only get an accurate reconstruction of the sampled signal when I'm within the defined max clock division value of 0-127. However, in the documentation it says that the clock divider can be from divide by 0 to divide by 32768. I'm mainly wondering why in CSL_SAR.h it is defined as 127 but in the documentation as 32768. This affects me currently because the usable bandwidth of my signal mainly falls within 0-100Hz so in reality the minimum sampling frequency I can choose of approx. 24,400Hz is overkill but with a larger divider the sampling frequency can be set to a much more reasonable value. Any advice is appreciated.

Thanks,

Ulbert 

  • 0
    TI__Genius 12575 points

    Hi,

    The documentation holds good, looks like the CSL_SAR.h clock divider check was implemented taking certain nominal scenarios, but wouldn't accommodate all, noted this for further changes.  

    Hope this clarifies.

    Regards

     Vasanth